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[ak4671] ms0666-e-02 2010/06 - 1 - general description the ak4671 is a stereo codec with a built-i n microphone-amplifier, receiver-amplifier and headphone-amplifier. the ak4671 featur es dual pcm i/f in addition to audio i/f that allows easy interfacing in mobile phone designs with bluetooth i/f. the ak4671 is av ailable in a 57pin bga, utilizing less board space than competitive offerings. features 1. recording function (stereo codec) ? 4 stereo input selector x 2ch ? 4 stereo inputs (single-ended) or 2 stereo input (full-differential) ? mic amplifier: +30db ? 12db, 3db step ? digital alc (automatic level control): +36db ? 54db, 0.375db step, mute ? wind-noise reduction filter ? stereo separation emphasis ? 5-band programmable notch filter ? audio interface format: 16bit msb justified, i 2 s, dsp mode 2. playback function (stereo codec) ? digital volume (+12db ? 115.0db, 0.5db step, mute) ? digital alc (automatic level control): +36db ? 54db, 0.375db step, mute ? stereo separation emphasis ? 5-band eq ? stereo line output ? mono receiver-amp - btl output - output power: 30mw@32 (avdd=3.3v) ? stereo headphone-amp - output power: 30mw@16 (avdd=3.3v) ? analog mixing: 4 stereo input ? audio interface format: - 16bit msb justified, 16bit lsb justified, 16-24bit i 2 s, dsp mode 3. dual pcm i/f for baseband & bluetooth interface ? sample rate converter (up sample: up to x6: down sample: down to x1/6) ? sample rate: 8khz ? digital volume ? audio interface format: - 16bit linear, 8bit a-law, 8bit -law - short/long frame, i 2 s, msb justified 4. 10bit sar adc ? 3 input selector 5. power management 6. master clock: (1) pll mode ? frequencies: 11.2896mhz, 12mhz, 12.288mhz, 13mhz, 13. 5mhz, 19.2mhz, 24mhz, 26mhz, 27mhz (mcki pin) 1fs (lrck pin) 32fs or 64fs (bick pin) (2) external clock mode ? frequencies: 256fs, 384fs, 512fs, 768fs or 1024fs (mcki pin) 7. output master clock fr equencies: 32fs/64fs/128fs/256fs 8. sampling rate (stereo codec): stereo codec with mic/rcv/hp- a mp ak4671
[ak4671] ms0666-e-02 2010/06 - 2 - ? pll slave mode (lrck pin): 8khz 48khz ? pll slave mode (bick pin): 8khz 48khz ? pll slave mode (mcki pin): 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? pll master mode: 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? ext master/slave mode: 8khz 48khz (256fs, 384fs), 8khz 26khz (512fs, 768fs), 8khz 13khz (1024fs) 9. p i/f: 4-wire serial / i 2 c bus (ver 1.0, 400khz fast mode) 10. master/slave mode 11. ta = ? 30 85 c 12. power supply: ? avdd, pvdd, savdd: 2.2 3.6v ? dvdd, tvdd2, tvdd3: 1.6 3.6v 13. package : 57pin bga (5mm x 5mm, 0.5mm pitch) block diagram mic power supply mic-amp pmmicl pmmicr audio i/f pmlo2 pmro2 internal mic external mic stereo line out or mono receiver headphone out pmlo3 pll pmpll mpw r lin1/in1+ rin1/in1 ? lin2/in2+ rin2/in2 ? lout2 rout2 lout3/lo p a vdd vss1 vcom dvdd i2c cdto bick lrck sdto sdti mcko mcki vcoc pmlo1 lout1/rc p rout1/rcn vss4 pmmp pmainl1 pmro3 rout3/lon pcm i/f a bicka synca sdtoa sdtia sain1 sain 3 a/d pmsad control register cclk/scl cdti/sda csn pcm i/f b sdtob sdtib rin3/in3 ? lin4/in4+ rin4/in4 ? lin3/in3+ bickb syncb tvdd2 tvdd 3 sain2 pmsra pmsrb stereo line out pllbt pmpcm vcocbt a/d stereo separation pmadl or pmadr d/a m i x pmdal or pmdar or pmsra alc 5-band notch datt smute pfsel=0 pmadl or pmadr pfsel=1 pmdal or pmdar or pmsra lpf hpf pdn mute t md t gpo1 pmro1 pmainr1 pmainl2 pmainr2 pmainl3 pmainr3 pmainl4 pmainr4 pmloopl pmloopr pvdd vss2 savd d vss 3 src-a src-b datt-c datt-b svolb gpo2 hpf mix svola 5-band eq s e l bvol pmdal or pmdar pmlo2s pmro2s figure 1. block diagram
[ak4671] ms0666-e-02 2010/06 - 3 - ordering guide ak4671eg ? 30 +85 c 57pin bga (0.5mm pitch) akd4671 evaluation board for ak4671 pin layout a top view bc e dfghj 6 7 8 9 5 3 4 1 2 ak4671 9 test lout2 rout2 vcom vc ocbt vss2 sdtoa synca gpo2 8 avdd vss1 mutet vcoc pvdd tvdd2 bicka cdti /sda sdtia 7 lout1 /rcp rout1 /rcn vss4 dvdd 6 rout3 /lon lout3 /lop cclk /scl csn /cad0 5 rin4 /in4 ? lin4 /in4+ top view i2c bick 4 lin3 /in3+ rin3 /in3 ? mcki mcko 3 lin2 /in2+ rin2 /in2 ? nc pdn lrck 2 lin1 /in1+ rin1 /in1 ? sain2 savdd tvdd3 sdtob bickb sdto cdto 1 mdt mpwr sain3 sain1 vss3 syncb sdtib sdti gpo1 a b c d e f g h j
[ak4671] ms0666-e-02 2010/06 - 4 - pin/function no. pin name i/o function a1 mdt i mic detection pin (internal pull down by 500k ) b1 mpwr o mic power supply pin c1 sain3 i 10bit sar adc analog input 3 pin c2 sain2 i 10bit sar adc analog input 2 pin d1 sain1 i 10bit sar adc analog input 1 pin d2 savdd - 10bit sar adc power supply pin, 2.2 3.6v e1 vss3 - ground 3 pin e2 tvdd3 - digital i/o power supply 3 pin, 1.6 3.6v f2 sdtob o serial data output b pin f1 syncb i/o sync signal b pin g2 bickb i/o serial data clock b pin g1 sdtib i serial data input b pin h1 sdti i audio serial data input pin j1 gpo1 o general purpose output 1 pin j2 cdto o control data output pin (i2c pin = ?l?: 4-wire serial mode) hi-z (i2c pin = ?h?: i 2 c bus mode) h2 sdto o audio serial data output pin h3 pdn i power-down mode pin ?h?: power-up, ?l?: power-down, reset and initializes the control register. ?l? time of 150ns or more after power-up is needed to reset the ak4671. j3 lrck i/o input / output channel clock pin h4 mcki i external master clock input pin j4 mcko o master clock output pin h5 i2c i control mode select pin ?h?: i 2 c bus, ?l?: 4-wire serial j5 bick i/o audio serial data clock pin csn i chip select pin (i2c pin = ?l?: 4-wire serial mode) j6 cad0 i chip address 0 select pin (i2c pin = ?h?: i 2 c bus mode) cclk i control data clock pin (i2c pin = ?l?: 4-wire serial mode) h6 scl i control data clock pin (i2c pin = ?h?: i 2 c bus mode) h7 vss4 - ground 4 pin j7 dvdd - digital power supply pin, 1.6 3.6v cdti i control data input pin (i2c pin = ?l?: 4-wire serial mode) h8 sda i/o control data input pin (i2c pin = ?h?: i 2 c bus mode) j9 gpo2 o general purpose output 2 pin
[ak4671] ms0666-e-02 2010/06 - 5 - no. pin name i/o function j8 sdtia i serial data input a pin g8 bicka i/o serial data clock a pin h9 synca i/o sync signal a pin g9 sdtoa o serial data output a pin f8 tvdd2 - digital i/o power supply 2 pin, 1.6 3.6v f9 vss2 - ground 2 pin e8 pvdd - pllbt power supply pin, 2.2 3.6v e9 vcocbt o output pin for loop filter of pllbt circuit this pin should be connected to vss2 pin with one resistor and capacitor in series. d8 vcoc o output pin for loop filter of pll circuit this pin should be connected to vss1 pin with one resistor and capacitor in series. d9 vcom o common voltage output pin, 0.5 x avdd bias voltage of adc inputs and dac outputs. c8 mutet o mute time constant control pin connected to vss1 pin with a capacitor for mute time constant. c9 rout2 o rch headphone-amp output pin b9 lout2 o lch headphone-amp output pin a9 test - test pin this pin should be open. a8 avdd - analog power supply pin, 2.2 3.6v b8 vss1 - ground 1 pin rout1 o rch stereo line output 1 pin (rcv bit = ?0?: stereo line output) b7 rcn o receiver-amp negative output pin ( rcv bit = ?1?: receiver output) lout1 o lch stereo line output 1 pin (rcv bit = ?0?: stereo line output) a7 rcp o receiver-amp positive output pin ( rcv bit = ?1?: receiver output) rout3 o rch stereo line output 3 pin (lodif bit = ?0?: single-ended stereo output) a6 lon o negative line output pin (lodif bit = ?1?: full-differential mono output) lout3 o lch stereo line output 3 pin (lodif bit = ?0?: single-ended stereo output) b6 lop o positive line output pin (lodif bit = ?1?: full-differential mono output) rin4 i rch analog input 4 pin (mdif4 bit = ?0?: single-ended input) a5 in4 ? i negative line input 4 pin (mdif4 bit = ?1?: full-differential input) lin4 i lch analog input 4 pin (mdif4 bit = ?0?: single-ended input) b5 in4+ i positive line input 4 pin (mdi f4 bit = ?1?: full-differential input) rin3 i rch analog input 3 pin (mdif3 bit = ?0?: single-ended input) b4 in3 ? i negative line input 3 pin (mdif3 bit = ?1?: full-differential input) lin3 i lch analog input 3 pin (mdif3 bit = ?0?: single-ended input) a4 in3+ i positive line input 3 pin (mdi f3 bit = ?1?: full-differential input) rin2 i rch analog input 2 pin (mdif2 bit = ?0?: single-ended input) b3 in2 ? i negative line input 2 pin (mdif2 bit = ?1?: full-differential input) lin2 i lch analog input 2 pin (mdif2 bit = ?0?: single-ended input) a3 in2+ i positive line input 2 pin (mdi f2 bit = ?1?: full-differential input) rin1 i rch analog input 1 pin (mdif1 bit = ?0?: single-ended input) b2 in1 ? i negative line input 1 pin (mdif1 bit = ?1?: full-differential input) lin1 i lch analog input 1 pin (mdif1 bit = ?0?: single-ended input) a2 in1+ i positive line input 1 pin (mdi f1 bit = ?1?: full-differential input) c3 nc - no connect pin no internal bonding. this pin should be open or connected to the ground. note 1. all input pins except analog input pins (mdt, lin1/in1+, rin1/in1 ? , lin2/in2+, rin2/in2 ? , lin3/in3+, rin3/in3 ? , lin4/in4+, rin4/in4 ? , sain1, sain2, sain3) should not be left floating. i/o pins except sda pin (lrck, bick, synca, bicka, syncb, bickb) should be processed appropriately. please refer the ? master mode/slave mode ? (p.45) and ? pcm i/f master mode/slave mode ? (p.105). sda pin should be pulled-up by a resistor externally a nd be connected to (dvdd+0.3)v or less voltage.
[ak4671] ms0666-e-02 2010/06 - 6 - handling of unused pin on the system the unused i/o pins on the system should be processed appropriately as below. classification pin name setting analog mpwr, mdt, vcoc, rout 3/lon, lout3/lop, rout2, lout2, mutet, rout1/rcn, lout1/rcp, rin4/in4 ? , lin4/in4+, rin3/in3 ? , lin3/in3+, rin2/in2 ? , lin2/in2+, rin1/in1 ? , lin1/in1+, vcocbt, sain1, sain2, sain3 these pins should be open. mcko, sdtoa, sdtob, gpo1, gpo2, cdto these pins should be open. mcki, sdtia, sdtib these pins should be connected to vss4. digital bicka, synca, bickb, syncb when all pins are unused, these pins should be connected to vss4 and pmpcm bit must be always ?0?. when either pcm i/f a(bicka/ synca) or pcm i/f b(bickb/syncb) is used, unused pins are connected to pull-down/up resistor of about 100k .
[ak4671] ms0666-e-02 2010/06 - 7 - absolute maximum ratings (vss1=vss2=vss3=vss4=0v; note 2 , note 3 ) parameter symbol min max units power supplies: analog avdd ? 0.3 4.0 v pllbt pvdd ? 0.3 4.0 v 10bit sar adc savdd ? 0.3 4.0 v digital dvdd ? 0.3 4.0 v digital i/o 2 tvdd2 ? 0.3 4.0 v digital i/o 3 tvdd3 ? 0.3 4.0 v input current, any pin except supplies iin - 10 ma analog input voltage 1 ( note 4 ) vina1 ? 0.3 avdd+0.3 v analog input voltage 2 ( note 5 ) vina2 ? 0.3 savdd+0.3 v digital input voltage 1 ( note 6 ) vind1 ? 0.3 dvdd+0.3 v digital input voltage 2 ( note 7 ) vind2 ? 0.3 tvdd2+0.3 v digital input voltage 3 ( note 8 ) vind3 ? 0.3 tvdd3+0.3 v ambient temperature (powered applied) ta ? 30 85 c storage temperature tstg ? 65 150 c note 2. all voltages with respect to ground. note 3. vss1, vss2, vss3 and vss4 must be connected to the same analog ground plane. note 4. rin4/in4 ? , lin4/in4+, rin3/in3 ? , lin3/in3+, rin2/in2 ? , lin2/in2+, rin1/in1 ? , lin1/in1+ pins note 5. sain1, sain2, sain3 pins note 6. pdn, i2c, csn/cad0, cclk/scl, cdti/sda, sdti, lrck, bick, mcki pins pull-up resistors at sda and scl pins should be connected to (dvdd+0.3)v or less voltage. note 7. bicka, synca, sdtia pins note 8. bickb, syncb, sdtib pins warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operating conditions (vss1=vss2=vss3=vss4=0v; note 2 ) parameter symbol min typ max units power supplies analog avdd 2.2 3.3 3.6 v ( note 9 ) pllbt pvdd 2.2 3.3 3.6 v 10bit sar adc savdd 2.2 3.3 3.6 v digital dvdd 1.6 3.3 3.6 v digital i/o 2 tvdd2 1.6 3.3 3.6 v digital i/o 3 tvdd3 1.6 3.3 3.6 v difference avdd ? pvdd ? 0.1 0 +0.1 v note 2. all voltages with respect to ground. note 9. the power-up sequence between avdd, pvdd, savdd, dvdd, tvdd2 and tvdd3 is not critical. the pdn pin should be held to ?l? when power-up. the p dn pin should be set to ?h? after all power supplies are powered-up. the ak4671 should be operated by th e recommended power-up/down sequence shown in ? system design (grounding and power supply decoupling) ? to avoid pop noise at recei ver output, hea dphone output and line output. when the power is off partially except for dvdd, a ll power management bits (pmvcm, pmmp, pmmicl, pmmicr, pmadl, pmadr, pmdal, pmdar, pmpll, pmloopl, pmloopr, pmainl1, pmainr1, pmainl2, pmainr2, pmainl3, pmainr3, pmainl4, pmainr4, pmlo1, pmro1, pmlo2, pmro2, pmlo2s, pmro2s, pmlo3, pmro3, pmsra, pmsrb, pmpcm, pmsad) should be ?0? or the pdn pin should be ?l?. dvdd should not be powered off while avdd, pvdd, savdd, tvdd2 or tvdd3 is powered on. when only dvdd is off, the current of 10ma to 100ma around may occur. * akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak4671] ms0666-e-02 2010/06 - 8 - analog characteristics (codec) (ta=25 c; avdd=pvdd=savdd=dvdd=tvdd2=tvdd3=3.3 v; vss1=vss2=vss3=vss4=0v; signal frequency=1khz; 16bit data; fs=44.1kh z, bick=64fs; measurement frequency=20hz 20khz; unless otherwise specified) parameter min typ max units mic amplifier: lin1/rin1/lin2/rin2/lin3/rin3/lin4/rin4 pins; pmainl1/r1/l2/r2/l3/r3/l4/r4 bits = ?0? input resistance mgnl/r0 bit = ?0? 28 42 56 k mgnl/r0 bit = ?1? 20 30 40 k gain ( note 10 ) max (mgnl/r3-0 bits = ?fh?) - +30 - db min (mgnl/r3-0 bits = ?1h?) - ? 12 - db mic power supply: mpwr pin output voltage ( note 11 ) 2.47 2.64 2.81 v load resistance 0.5 - - k load capacitance - - 30 pf mic detection: mdt pin comparator voltage level ( note 12 ) 0.165 0.247 mv internal pull down resistance 250 500 750 k stereo adc analog input characteristics: lin1/rin1/lin2/rin2/lin3/rin3/lin4/rin4 pins stereo adc ivol, ivol=0db, alc=off resolution - - 16 bits ( note 14 ) 0.150 0.176 0.203 vpp input voltage ( note 13 ) ( note 15 ) 1.68 1.98 2.28 vpp ( note 14 ) 72 82 - db s/(n+d) ( ? 1dbfs) ( note 15 ) - 87 - db ( note 14 ) 75 85 - db d-range ( ? 60dbfs, a-weighted) ( note 15 ) - 95 - db ( note 14 ) 75 85 - db s/n (a-weighted) ( note 15 ) - 95 - db ( note 14 ) 75 90 - db interchannel isolation ( note 15 ) - 100 - db ( note 14 ) - 0.1 0.8 db interchannel gain mismatch ( note 15 ) - 0.1 0.8 db note 10. in case of full-differential i nput, mgain=0db (min) and avdd=2.4v (min). note 11. output voltage is proportional to avdd voltage. vout = 0.8 x avdd (typ). note 12. comparator voltage level is proportional to avdd voltage. vth = 0.05 x avdd(min), 0.075 x avdd(max). note 13. input voltage is proportional to avdd volta ge. vin = 0.053 x avdd (typ)@mgnl3-0=mgnr3-0 bits = ?ch? (+21db), vin = 0.6 x avdd(typ)@mgnl 3-0=mgnr3-0 bits = ?5h? (0db). note 14. mgnl3-0=mgnr3-0 bits = ?ch? (+21db). note 15. mgnl3-0=mgnr3-0 bits = ?5h? (0db).
[ak4671] ms0666-e-02 2010/06 - 9 - parameter min typ max units stereo dac characteristics: resolution - - 16 bits stereo line output characteristics: stereo dac lout1/rout1/lout3/ rout3 pins, alc=off, ivol= 0db, ovol=0db, l1vl=l3vl=0db, rcv bit = ?0?, r l =10k ; unless otherwise specified. output voltage ( note 16 ) 1.78 1.98 2.18 vpp s/(n+d) (0dbfs) 75 85 - db s/n (a-weighted) 82 92 - db interchannel isolation 85 100 - db interchannel gain mismatch - 0.1 0.8 db load resistance 10 - - k load capacitance - - 30 pf mono receiver-amp output characteristics: stereo dac rcp/rcn pins, alc=off, ivol=0db, ovol=0db, l1vl=0db, rcv bit = ?1?, r l =32 , btl; unless otherwise specified. output voltage ( note 17 ) ? 6dbfs, r l =32 (po=15mw) 1.76 1.96 2.16 vpp ? 3dbfs, r l =32 (po=30mw) - 2.77 - vpp s/(n+d) ? 6dbfs, r l =32 (po=15mw) 40 60 - db ? 3dbfs, r l =32 (po=30mw) - 20 - db s/n (a-weighted) 82 92 - db load resistance 32 - - load capacitance ( note 18 ) - - 30 pf headphone-amp characteristics: dac lout2/rout2 pins, alc=off, ivol=0db, ovol =0db, hpg=0db, r l =16 output voltage ( note 19 ) ? 6dbfs (po=7.6mw) 0.89 0.99 1.09 vpp 0dbfs (po=30mw) - 1.98 - vpp s/(n+d) ? 6dbfs (po=7.6mw) 40 60 - db 0dbfs (po=30mw) - 40 - db s/n (a-weighted) 80 90 - db interchannel isolation 65 75 - db interchannel gain mismatch - 0.1 0.8 db load resistance 16 - - c1 in figure 2 - - 30 pf load capacitance c2 in figure 2 - - 300 pf note 16. output voltage is proportional to avdd voltage. vout = 0.6 x avdd (typ). note 17. output voltage is proportional to avdd voltage. vout = (rcp) ? (rcn) = 0.59 x avdd (typ)@ ? 6dbfs. note 18. load capacitance for vss1. note 19. output voltage is proportional to avdd voltage. vout = 0.3 x avdd (typ)@ ? 6dbfs.
[ak4671] ms0666-e-02 2010/06 - 10 - lout2 pin rout2 pin hp-amp 100 f c1 16 c2 0.22 f 10 measurement point figure 2. headphone-amp output circuit parameter min typ max units mono line output characteristics: stereo dac lop/lon pins, alc=o ff, ivol=0db, ovol=0db, l3vl=0db, lodif bit = ?1?, r l =10k for each pin (full-differential) output voltage ( note 20 ) 3.52 3.96 4.36 vpp s/(n+d) (0dbfs) 75 85 - db s/n (a-weighted) 85 95 - db load resistance (lop/lon pins, respectively) 10 - - k load capacitance (lop/lon pins, respectively) ( note 21 ) - - 30 pf single-ended line input: lin1/rin1/lin2/rin2/lin3/rin3/lin4/rin4 pins; (mdif1=mdif2=mdif3=mdif4 bits = ?0?) maximum input voltage ( note 22 ) - 1.98 - vpp gain input ? lout1/rout1/lout 2/rout2/lout3/r out3 (lodif=rcv bits = ?0?) ? 1 0 +1 db input ? rcp/rcn/lop/lon (lodif=rcv bits = ?1?) - +6 - db full-differential line input: in1+/ ? , in2+/ ? , in3+/ ? , in4+/ ? pins; (mdif1=mdif2=mdif3=mdif4 bits = ?1?) maximum input voltage ( note 23 ) - 1.98 - vpp gain input ? lout1/rout1/lout 2/rout2/lout3/r out3 (lodif=rcv bits = ?0?) ? 1 0 +1 db input ? rcp/rcn/lop/lon (lodif=rcv bits = ?1?, note 24 ) - +6 - db power supply current: power up (pdn pin = ?h?, all circuits power-up) ( note 25 ) - 21 - ma ( note 26 ) - 23 30 ma avdd+pvdd+dvdd +tvdd2+tvdd3+savdd ( note 27 ) - 8 12 ma power down (pdn pin = ?l?) ( note 28 ) avdd+pvdd+dvdd +tvdd2+tvdd3+savdd - 1 30 a note 20. output voltage is proportional to avdd voltage. vout = (lop) ? (lon) = 1.2 x avdd (typ). note 21. load capacitance for vss1. note 22. maximum input voltage which analog output does not clip is proportional to avdd voltage. vin = 0.6 x avdd (typ). note 23. maximum input voltage which analog output does not clip is proportional to avdd voltage. vin = (in4+) ? (in4 ? ) = 0.6 x avdd (typ). note 24. vout = (rcp) ? (rcn) at rcv bit = ?1?, vout = (lop) ? (lon) at lodif bit = ?1?. note 25. ext slave mode and lp bit = ?0?, fs=44.1khz, pmmicl = pmmicr = pmadl = pmadr = pmdal = pmdar = pmlo1 = pmro1 = pmlo2 = pmro2 = pm lo2s = pmro2s = pmlo3 = pmro3 =pmsad =
[ak4671] ms0666-e-02 2010/06 - 11 - pmvcm = muten bits = ?1?, pmpll = mcko = pmmp = m/s = pmsra = pmsrb = pmpcm bits = ?0?. avdd=13.2ma (typ), pvdd=0ma (typ ), dvdd=6.7ma (typ), tvdd2=0ma (typ), tvdd3=0ma (typ), savdd=0.8ma (typ). note 26. pll master mode and lp bit = ?0?, fs=44.1khz, pmadl = pmmicl= pmmicr= pmadr = pmdal = pmdar = pmlo1 = pmro1 = pmlo2 = pmro2 = pm lo2s = pmro2s = pmlo3 = pmro3 =pmsad = pmvcm = pmpll = m/s = pmmp = muten bits = ?1 ?, mcko = pmsra = pmsrb = pmpcm bits = ?0?, pll reference clock = mcki = 11.2896mhz. avdd=14.7ma (typ), pvdd=0ma (typ ), dvdd=7.0ma (typ), tvdd2=0ma (typ), tvdd3=0ma (typ), savdd=0.8ma (typ). note 27. in case of lp bit = ?1?, fs=8khz, ext slav e mode and pmvcm = pmmp = pmmicl = pmadl = pmdar = rcv = pmlo1 = pmro1 = pmsra = pmsrb = pmpcm bits = ?1?. avdd=5.2ma (typ), pvdd=0.6ma (typ ), dvdd=2.2ma (typ), tvdd2=0ma (typ), tvdd3=0ma (typ), savdd=0ma (typ). note 28. all digital input pins are fixed to each supply pin (dvdd, tvdd2 or tvdd3) or vss4. src characteristics (ta=25 c; avdd=pvdd=savdd=dvdd=tvdd2=tvdd3=3.3 v; vss1=vss2=vss3=vss4=0v; signal frequency=1khz; 16bit data; measurement frequency=20hz 3.4khz; unless otherwise specified) parameter symbol min typ max units src characteristics (down sampling: src-a): sdti ? src-a ? sdtoa/sdtob resolution - - 16 bits input sample rate fsi (fs) 8 - 48 khz output sample rate fso (fs2) - 8 - khz thd+n (input = 1khz, ? 1dbfs, note 29 ) fso/fsi = 8khz/44.1khz - ? 94 - db dynamic range (input = 1khz, ? 60dbfs, note 29 ) fso/fsi = 8khz/44.1khz - 97 - db ratio between input and output sample rate fso/fsi 1/6 1 - src characteristics (up sampling: src-b): sdtia/sdtib ? src-b ? sdto resolution - - 16 bits input sample rate fsi (fs2) - 8 - khz output sample rate fso (fs) 8 - 48 khz thd+n (input = 1khz, ? 1dbfs, note 29 ) fso/fsi = 44.1khz/8khz - ? 95 - db dynamic range (input = 1khz, ? 60dbfs, note 29 ) fso/fsi = 44.1khz/8khz - 100 - db ratio between input and output sample rate fso/fsi 1 6 - note 29. measured by audio precision system two cascade. note 30. fs is the sampling frequency fo r stereo codec. fs2 is for pcm i/f.
[ak4671] ms0666-e-02 2010/06 - 12 - analog characteristics (10bit sar adc) (ta=25 c; avdd=pvdd=savdd=dvdd =tvdd2 =tvdd3=3.3v; vss1=vss2=vss3=vss4=0v; unless otherwise specified) parameter min typ max units 10bit sar adc characteristics resolution - 10 - bits no missing codes 9 10 - bits integral linearity error - - 2 lsb dnl - 1 - lsb analog input voltage range 0 - savdd v offset error - - 3 lsb gain error - - 2 lsb accuracy ( note 31 ) - - 1 % note 31. accuracy is the difference between the output code when 1.1v is input to sain1, sain2 or sain3 pin and the ?ideal? code at 1.1v. filter characteristics (codec) (ta=25 c; avdd=pvdd =savdd=2.2 3.6v; dvdd=tvdd2 =tvdd3=1.6 3.6v; fs=44.1khz; programmable filter=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 32 ) 0.16db pb 0 - 17.3 khz ? 0.66db - 19.4 - khz ? 1.1db - 19.9 - khz ? 6.9db - 22.1 - khz stopband sb 25.9 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 69 - - db group delay ( note 33 ) gd - 19 - 1/fs group delay distortion gd - 0 - s dac digital filter (lpf): passband ( note 32 ) 0.1db pb 0 - 17.4 khz ? 1.0db - 20.0 - khz ? 3.0db - 21.1 - khz stopband sb 25.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay ( note 33 ) gd - 19 - 1/fs dac digital filter (lpf) + scf: frequency response: 0 20.0khz fr - 1.4 - db note 32. the passband and stopband frequencies scale with fs (system sampling rate). for example, dac is pb=0.454 x fs (@ ? 0.7db). each response refers to that of 1khz. note 33. the calculated delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the adc. for the dac, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal.
[ak4671] ms0666-e-02 2010/06 - 13 - filter characteristics (src) (ta=25 c; avdd=pvdd = savdd=2.2 3.6v; dvdd=tvdd2 =tvdd3=1.6 3.6v; fs2=8khz; programmable filter=off) parameter symbol min typ max units down sampling (src-a): fs=8khz passband 0.15db pb 0 - 3.0 khz stopband sb 4.7 - - khz passband ripple pr - - 0.15 db stopband attenuation sa 69 - - db group delay ( note 34 ) gd - 5 - ms down sampling (src-a): fs=11.025khz passband 0.15db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.15 db stopband attenuation sa 69 - - db group delay ( note 34 ) gd - 4 - ms down sampling (src-a): fs=12khz passband 0.15db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.15 db stopband attenuation sa 69 - - db group delay ( note 34 ) gd - 4 - ms down sampling (src-a): fs=16khz passband 0.15db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.15 db stopband attenuation sa 69 - - db group delay ( note 34 ) gd - 3 - ms down sampling (src-a): fs=22.05khz passband 0.15db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.15 db stopband attenuation sa 69 - - db group delay ( note 34 ) gd - 3 - ms down sampling (src-a): fs=24khz passband 0.15db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.15 db stopband attenuation sa 69 - - db group delay ( note 34 ) gd - 3 - ms note 34. the calculated delay time caused by digital filteri ng. this time is from setting the 16-bit data from the input register to the output register.
[ak4671] ms0666-e-02 2010/06 - 14 - parameter symbol min typ max units down sampling (src-a): fs=32khz passband 0.1db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 69 - - db group delay ( note 34 ) gd - 3 - ms down sampling (src-a): fs=44.1khz passband 0.1db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 69 - - db group delay ( note 34 ) gd - 3 - ms down sampling (src-a): fs=48khz passband 0.1db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 69 - - db group delay ( note 34 ) gd - 3 - ms note 34. the calculated delay time caused by digital filteri ng. this time is from setting the 16-bit data from the input register to the output register.
[ak4671] ms0666-e-02 2010/06 - 15 - parameter symbol min typ max units up sampling (src-b): fs=8khz passband 0.1db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay ( note 34 ) gd - 2 - ms up sampling (src-b): fs=11.025khz passband 0.1db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay ( note 34 ) gd - 2 - ms up sampling (src-b): fs=12khz passband 0.1db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay ( note 34 ) gd - 2 - ms up sampling (src-b): fs=16khz passband 0.1db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay ( note 34 ) gd - 2 - ms up sampling (src-b): fs=22.05khz passband 0.1db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay ( note 34 ) gd - 2 - ms up sampling (src-b): fs=24khz passband 0.1db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay ( note 34 ) gd - 2 - ms note 34. the calculated delay time caused by digital filteri ng. this time is from setting the 16-bit data from the input register to the output register.
[ak4671] ms0666-e-02 2010/06 - 16 - parameter symbol min typ max units up sampling (src-b): fs=32khz passband 0.1db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay ( note 34 ) gd - 2 - ms up sampling (src-b): fs=44.1khz passband 0.1db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay ( note 34 ) gd - 2 - ms up sampling (src-b): fs=48khz passband 0.1db pb 0 - 3.1 khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay ( note 34 ) gd - 2 - ms note 34. the calculated delay time caused by digital filteri ng. this time is from setting the 16-bit data from the input register to the output register.
[ak4671] ms0666-e-02 2010/06 - 17 - dc characteristics (ta=25 c; avdd=pvdd =savdd=2.2 3.6v; dvdd=tvdd2 =tvdd3=1.6 3.6v) parameter symbol min typ max units high-level input voltage 1 2.2v dvdd 3.6v vih1 70 % dvdd - - v ( note 35 ) 1.6v dvdd<2.2v vih1 80 % dvdd - - v low-level input voltage 1 2.2v dvdd 3.6v vil1 - - 30 % dvdd v ( note 35 ) 1.6v dvdd<2.2v vil1 - - 20 % dvdd v high-level input voltage 2 2.2v tvdd2 3.6v vih2 70 % tvdd2 - - v ( note 36 ) 1.6v tvdd2<2.2v vih2 80 % tvdd2 - - v low-level input voltage 2 2.2v tvdd2 3.6v vil2 - - 30 % tvdd2 v ( note 36 ) 1.6v tvdd2<2.2v vil2 - - 20 % tvdd2 v high-level input voltage 3 2.2v tvdd3 3.6v vih3 70 % tvdd3 - - v ( note 37 ) 1.6v tvdd3<2.2v vih3 80 % tvdd3 - - v low-level input voltage 3 2.2v tvdd3 3.6v vil3 - - 30 % tvdd3 v ( note 37 ) 1.6v tvdd3<2.2v vil3 - - 20 % tvdd3 v high-level output voltage ( note 38 ) (iout= ? 200 a) voh1 dvdd ? 0.2 - - v ( note 39 ) (iout= ? 200 a) voh2 tvdd2 ? 0.2 - - v ( note 40 ) (iout= ? 200 a) voh3 tvdd3 ? 0.2 - - v low-level output voltage (except sda pin: iout=200 a) vol1 - - 0.2 v (sda pin, 2.0v dvdd 3.6v: iout=3ma) vol2 - - 0.4 v (sda pin, 1.6v dvdd<2.0v: iout=3ma) vol2 - - 20%dvdd v input leakage current ( note 41 ) iind - - 2 a ( note 42 ) iina - - 2 a note 35. csn/cad0, cclk/scl, cdti/sda, i2c, pdn, bick, lrck, sdti, mcki pins. note 36. bicka, synca, sdtia pins. note 37. bickb, syncb, sdtib pins. note 38. mcko, bick, lrck, sdto, cdto, gpo1, gpo2 pins. note 39. bicka, synca, sdtoa pins. note 40. bickb, syncb, sdtob pins. note 41. syncb, bickb, sdtib, sdti, lrck, mcki, bick, csn/cad0, cclk/scl, cdti/sda, sdtia,bicka, synca pins. i/o pins (syncb, bickb, lrck, bick, sda, bicka, synca) are at the time of input state. note 42. sain1, sain2, sain3 pins.
[ak4671] ms0666-e-02 2010/06 - 18 - switching characteristics (ta=25 c; avdd=pvdd =savdd=2.2 3.6v; dvdd=tvdd2 =tvdd3=1.6 3.6v; c l =20pf (except sda pin) or 400pf (sda pin); unless otherwise specified) parameter symbol min typ max units pll master mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.256 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck output timing frequency fs 8 - 48 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - % pll slave mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.256 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck input timing frequency fs 8 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns
[ak4671] ms0666-e-02 2010/06 - 19 - parameter symbol min typ max units pll slave mode (pll reference clock = lrck pin) lrck input timing frequency fs 8 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns pll slave mode (pll reference clock = bick pin) lrck input timing frequency fs 8 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period pll3-0 bits = ?0010? tbck - 1/(32fs) - ns pll3-0 bits = ?0011? tbck - 1/(64fs) - ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns external slave mode mcki input timing frequency 256fs fclk 2.048 - 12.288 mhz 384fs fclk 3.072 - 18.432 mhz 512fs fclk 4.096 - 13.312 mhz 768fs fclk 6.144 - 19.968 mhz 1024fs fclk 8.192 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck input timing frequency 256fs/384fs fs 8 - 48 khz 512fs/768fs fs 8 - 26 khz 1024fs fs 8 - 13 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period tbck 312.5 - - ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns external master mode mcki input timing frequency 256fs fclk 2.048 - 12.288 mhz 384fs fclk 3.072 - 18.432 mhz 512fs fclk 4.096 - 13.312 mhz 768fs fclk 6.144 - 19.968 mhz 1024fs fclk 8.192 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck output timing frequency fs 8 - 48 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - %
[ak4671] ms0666-e-02 2010/06 - 20 - parameter symbol min typ max units audio interface timing (dsp mode) master mode lrck ? ? to bick ? ? ( note 43 ) tdbf 0.5 x tbck ? 40 0.5 x tbck 0.5 x tbck + 40 ns lrck ? ? to bick ? ? ( note 44 ) tdbf 0.5 x tbck ? 40 0.5 x tbck 0.5 x tbck + 40 ns bick ? ? to sdto (bckp bit = ?0?) tbsd ? 70 - 70 ns bick ? ? to sdto (bckp bit = ?1?) tbsd ? 70 - 70 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck ? ? to bick ? ? ( note 43 ) tlrb 0.4 x tbck - - ns lrck ? ? to bick ? ? ( note 44 ) tlrb 0.4 x tbck - - ns bick ? ? to lrck ? ? ( note 43 ) tblr 0.4 x tbck - - ns bick ? ? to lrck ? ? ( note 44 ) tblr 0.4 x tbck - - ns bick ? ? to sdto (bckp bit = ?0?) tbsd - - 80 ns bick ? ? to sdto (bckp bit = ?1?) tbsd - - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns audio interface timing (r ight/left justified & i 2 s) master mode bick ? ? to lrck edge ( note 45 ) tmblr ? 40 - 40 ns lrck edge to sdto (msb) (except i 2 s mode) tlrd ? 70 - 70 ns bick ? ? to sdto tbsd ? 70 - 70 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck edge to bick ? ? ( note 45 ) tlrb 50 - - ns bick ? ? to lrck edge ( note 45 ) tblr 50 - - ns lrck edge to sdto (msb) (except i 2 s mode) tlrd - - 80 ns bick ? ? to sdto tbsd - - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns note 43. msbs, bckp bits = ?00? or ?11?. note 44. msbs, bckp bits = ?01? or ?10?. note 45. bick rising edge must not occur at the same time as lrck edge.
[ak4671] ms0666-e-02 2010/06 - 21 - parameter symbol min typ max units pcm interface timing (bicka, synca, sdtia, sdtoa pins; slave mode): synca timing frequency fs2 - 8 - khz serial interface timing at short/long frame sync bicka frequency fbck2 128 - 2048 khz bicka period tbck2 488 - - ns bicka pulse width low tbckl2 200 - - ns pulse width high tbckh2 200 - - ns synca edge to bicka ? ? ( note 46 ) tsyb2 50 - - ns synca edge to bicka ? ? ( note 47 ) tsyb2 50 - - ns bicka ? ? to synca edge ( note 46 ) tbsy2 50 - - ns bicka ? ? to synca edge ( note 47 ) tbsy2 50 - - ns synca to sdtoa (msb) (except short frame) tsyd2 - - 80 ns bicka ? ? to sdtoa (bckpa bit = ?0?) tbsd2 - - 80 ns bicka ? ? to sdtoa (bckpa bit = ?1?) tbsd2 - - 80 ns sdtia hold time tsdh2 50 - - ns sdtia setup time tsds2 50 - - ns synca pulse width low tsyl2 0.8 x tbck2 - - ns pulse width high tsyh2 0.8 x tbck2 - - ns serial interface timing at msb justified and i 2 s bicka frequency fbck2 256 - 2048 khz bicka period tbck2 488 - - ns bicka pulse width low tbckl2 200 - - ns pulse width high tbckh2 200 - - ns synca edge to bicka ? ? tsyb2 50 - - ns bicka ? ? to synca edge tbsy2 50 - - ns synca to sdtoa (msb) (except i 2 s mode) tsyd2 - - 80 ns bicka ? ? to sdtoa tbsd2 - - 80 ns sdtia hold time tsdh2 50 - - ns sdtia setup time tsds2 50 - - ns synca duty cycle dsyc2 45 50 55 % note 46. msbsa, bckpa bits = ?00? or ?11?. note 47. msbsa, bckpa bits = ?01? or ?10?.
[ak4671] ms0666-e-02 2010/06 - 22 - parameter symbol min typ max units pcm interface timing (bicka, synca, sdtia, sdtoa pins; master mode): synca timing frequency fs2 - 8 - khz bicka timing period (bcko2 bit = ?0?) tbck2 - 1/(16fs2) - ns (bcko2 bit = ?1?) tbck2 - 1/(32fs2) - ns duty cycle dbck2 - 50 - % serial interface timing at short/long frame sync synca edge to bicka ? ? ( note 46 ) tsyb2 0.5 x tbck2 ? 40 0.5 x tbck2 0.5 x tbck2 + 40 ns synca edge to bicka ? ? ( note 47 ) tsyb2 0.5 x tbck2 ? 40 0.5 x tbck2 0.5 x tbck2 + 40 ns bicka ? ? to sdtoa (bckpa bit = ?0?) tbsd2 ? 70 - 70 ns bicka ? ? to sdtoa (bckpa bit = ?1?) tbsd2 ? 70 - 70 ns sdtia hold time tsdh2 50 - - ns sdtia setup time tsds2 50 - - ns synca pulse width high tsyh2 - tbck2 - ns serial interface timing at msb justified and i 2 s bicka ? ? to synca edge tmbsy2 ? 40 - 40 ns synca to sdtoa (msb) (except i 2 s mode) tsyd2 ? 70 - 70 ns bicka ? ? to sdtoa tbsd2 ? 70 - 70 ns sdtia hold time tsdh2 50 - - ns sdtia setup time tsds2 50 - - ns synca duty cycle dsyc2 - 50 - % note 46. msbsa, bckpa bits = ?00? or ?11?. note 47. msbsa, bckpa bits = ?01? or ?10?.
[ak4671] ms0666-e-02 2010/06 - 23 - parameter symbol min typ max units pcm interface timing (bickb, syncb , sdtib, sdtob pins; slave mode): syncb timing frequency fs2 - 8 - khz serial interface timing at short/long frame sync bickb frequency fbck3 128 - 2048 khz bickb period tbck3 488 - - ns bickb pulse width low tbckl3 200 - - ns pulse width high tbckh3 200 - - ns syncb edge to bickb ? ? ( note 48 ) tsyb3 50 - - ns syncb edge to bickb ? ? ( note 49 ) tsyb3 50 - - ns bickb ? ? to syncb edge ( note 48 ) tbsy3 50 - - ns bickb ? ? to syncb edge ( note 49 ) tbsy3 50 - - ns syncb to sdtob (msb) (except short frame) tsyd3 - - 80 ns bickb ? ? to sdtob (bck pb bit = ?0?) tbsd3 - - 80 ns bickb ? ? to sdtob (bck pb bit = ?1?) tbsd3 - - 80 ns sdtib hold time tsdh3 50 - - ns sdtib setup time tsds3 50 - - ns syncb pulse width low tsyl3 0.8 x tbck3 - - ns pulse width high tsyh3 0.8 x tbck3 - - ns serial interface timing at msb justified and i 2 s bickb frequency fbck3 256 - 2048 khz bickb period tbck3 488 - - ns bickb pulse width low tbckl3 200 - - ns pulse width high tbckh3 200 - - ns syncb edge to bickb ? ? tsyb3 50 - - ns bickb ? ? to syncb edge tbsy3 50 - - ns syncb to sdtob (msb) (except i 2 s mode) tsyd3 - - 80 ns bickb ? ? to sdtob tbsd3 - - 80 ns sdtib hold time tsdh3 50 - - ns sdtib setup time tsds3 50 - - ns syncb duty cycle dsyc3 45 50 55 % note 48. msbsb, bckpb bits = ?00? or ?11?. note 49. msbsb, bckpb bits = ?01? or ?10?.
[ak4671] ms0666-e-02 2010/06 - 24 - parameter symbol min typ max units pcm interface timing (bickb, syncb , sdtib, sdtob pins; master mode): syncb timing frequency fs2 - 8 - khz bickb timing period (bcko2 bit = ?0?) tbck3 - 1/(16fs2) - ns (bcko2 bit = ?1?) tbck3 - 1/(32fs2) - ns duty cycle dbck3 - 50 - % serial interface timing at short/long frame sync syncb edge to bickb ? ? ( note 48 ) tsyb3 0.5 x tbck3 ? 40 0.5 x tbck 3 0.5 x tbck3 + 40 ns syncb edge to bickb ? ? ( note 49 ) tsyb3 0.5 x tbck3 ? 40 0.5 x tbck 3 0.5 x tbck3 + 40 ns bickb ? ? to sdtob (bck pb bit = ?0?) tbsd3 ? 70 - 70 ns bickb ? ? to sdtob (bck pb bit = ?1?) tbsd3 ? 70 - 70 ns sdtib hold time tsdh3 50 - - ns sdtib setup time tsds3 50 - - ns syncb pulse width high tsyh3 - tbck3 - ns serial interface timing at msb justified and i 2 s bickb ? ? to syncb edge tmbsy3 ? 40 - 40 ns syncb to sdtob (msb) (except i 2 s mode) tsyd3 ? 70 - 70 ns bickb ? ? to sdtob tbsd3 ? 70 - 70 ns sdtib hold time tsdh3 50 - - ns sdtib setup time tsds3 50 - - ns syncb duty cycle dsyc3 - 50 - % note 48. msbsb, bckpb bits = ?00? or ?11?. note 49. msbsb, bckpb bits = ?01? or ?10?.
[ak4671] ms0666-e-02 2010/06 - 25 - parameter symbol min typ max units control interface timing (4-wire serial mode) cclk period ( note 51 ) tcck 200 - 33000 ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdti setup time tcds 40 - - ns cdti hold time tcdh 40 - - ns csn ?h? time tcsw 150 - - ns csn edge to cclk ? ? ( note 52 ) tcss 50 - - ns cclk ? ? to csn edge ( note 52 ) tcsh 50 - - ns cdto delay tdcd - - 70 ns csn ? ? to cdto hi-z tccz - - 70 ns control interface timing (i 2 c bus mode): ( note 50 ) scl clock frequency ( note 53 ) fscl 30 - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 54 ) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s capacitive load on bus cb - - 400 pf pulse width of spike noise suppressed by input filter tsp 0 - 50 ns power-down & reset timing pdn pulse width ( note 55 ) tpd 150 - - ns pmadl or pmadr ? ? to sdto valid ( note 56 ) tpdv - 1059 - 1/fs pmsra ? ? to sdtoa valid ( note 57 ) tpdv2 - 21 - 1/fs2 pmsrb ? ? to sdto valid ( note 58 ) tpdv3 - 135 - 1/fs note 50. i 2 c-bus is a trademark of nxp b.v. note 51. cclk should be input succeedi ngly until 10bit data of sar adc is r ead out at 4-wire serial mode ( figure 97 ). note 52. cclk rising edge must not occur at the same time as csn edge. note 53. in case that sar adc data is read out via i 2 c bus, scl should be input succeed ingly corresponding 2 byte data including ack ( figure 104 ). note 54. data must be held long enough to bridge the 300ns-transition time of scl. note 55. the ak4671 can be reset by bringing pdn pin = ?l? to ?h? only upon power up. note 56. this is the count of lrck ? ? from the pmadl or pmadr bit = ?1? at pmsrb bit = ?1?. note 57. the signal path is sdti src-a sdtoa and pllbt is locked. note 58. the signal path is sdtia src-b sdto.
[ak4671] ms0666-e-02 2010/06 - 26 - timing diagram lrck 1/fclk mcki tclkh tclkl vih1 vil1 1/fmck mcko tmckl 50%dvdd 1/fs tlrckh tlrckl 50%dvdd duty = tlrckh x fs x 100 tlrckl x fs x 100 dmck = tmckl x fmck x 100 bick tbck tbckh tbckl 50%dvdd dbck = tbckh / tbck x 100 tbckl / tbck x 100 figure 3. clock timing (pll/ext master mode) note 59. mcko is not available at ext master mode. lrck bick 50%dvdd sdto 50%dvdd tbsd tdbf 50%dvdd tlrckh msb bick 50%dvdd (bckp = "0") (bckp = "1") tsds sdti vil1 tsdh vih1 figure 4. audio interface timing (pll/ext master mode, dsp mode, msbs = ?0?)
[ak4671] ms0666-e-02 2010/06 - 27 - lrck bick 50%dvdd sdto 50%dvdd tbsd tdbf 50%dvdd tlrckh msb bick 50%dvdd (bckp = "1") (bckp = "0") tsds sdti vil1 tsdh vih1 figure 5. audio interface timing (pll/ext master mode, dsp mode, msbs = ?1?) lrck 50%dvdd bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih tmblr tlrd figure 6. audio interface timing (pll/ ext master mode, except dsp mode)
[ak4671] ms0666-e-02 2010/06 - 28 - 1/fs lrck vih1 tlrckh vil1 tbck bick tbckh tbckl vih1 vil1 tblr bick vih1 vil1 (bckp = "0") (bckp = "1") figure 7. clock timing (pll slave mode; pll reference clock = lrck or bick pin, dsp mode, msbs = ?0?) 1/fs lrck vih1 tlrckh vil1 tbck bick tbckh tbckl vih1 vil1 tblr bick vih1 vil1 (bckp = "1") (bckp = "0") figure 8. clock timing (pll slave mode; pll reference clock = lrck or bick pin, dsp mode, msbs = ?1?)
[ak4671] ms0666-e-02 2010/06 - 29 - 1/fclk mcki tclkh tclkl vih1 vil1 1/fs lrck vih1 vil1 tbck bick tbckh tbckl vih1 vil1 tlrckh tlrckl 1/fmck mcko tmckl 50%dvdd dmck = tmckl x fmck x 100 duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 9. clock timing (pll slave mode; except dsp mode) lrck bick sdto 50%dvdd tbsd tsds sdti vil1 tsdh vih1 tlrb tlrckh msb msb vil1 vih1 vil1 vih1 bick vil1 vih1 (bckp = "0") (bckp = "1") figure 10. audio interface timing (pll slave mode, dsp mode; msbs = ?0?)
[ak4671] ms0666-e-02 2010/06 - 30 - lrck bick sdto 50%dvdd tbsd tsds sdti vil1 tsdh vih1 tlrb tlrckh msb msb vil1 vih1 vil1 vih1 bick vil1 vih1 (bckp = "1") (bckp = "0") figure 11. audio interface timing (pll slave mode, dsp mode, msbs = ?1?) 1/fclk mcki tclkh tclkl vih1 vil1 1/fs lrck vih1 vil1 tbck bick tbckh tbckl vih1 vil1 tlrckh tlrckl duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 12. clock timing (ext slave mode)
[ak4671] ms0666-e-02 2010/06 - 31 - lrck vih1 vil1 tblr bick vih1 vil1 tlrd sdto 50%dvdd tlrb tbsd tsds sdti vil1 tsdh vih1 msb figure 13. audio interface timing (pll/ ext slave mode, except dsp mode) 1/fs2 vih2 vil2 synca tsyh2 tsyl2 dsyc2 = tsyh2 x fs2 x 100 tsyl2 x fs2 x 100 tbck2 = 1/fbck2 tbckl2 vih2 tbckh2 vil2 bicka figure 14. clock timing of pcm i/f a (slave mode)
[ak4671] ms0666-e-02 2010/06 - 32 - tsyb2 synca vih2 bicka vil2 sdtoa 50%tvdd2 tbsd2 vih2 vil2 tbsy2 tsds2 sdtia vih2 vil2 tsdh2 tsyd2 vih2 bicka vil2 (bckpa = ?0?) (bckpa = ?1?) figure 15. pcm i/f a timing at short and long frame sync (slave mode; msbsa = ?0?) tsyb2 synca vih2 bicka vil2 sdtoa 50%tvdd2 tbsd2 vih2 vil2 tbsy2 tsds2 sdtia vih2 vil2 tsdh2 vih2 bicka vil2 (bckpa = ?1?) (bckpa = ?0?) figure 16. pcm i/f a timing at short and long frame sync (slave mode; msbsa = ?1?)
[ak4671] ms0666-e-02 2010/06 - 33 - tsyb2 synca vih2 bicka vil2 sdtoa 50%tvdd2 tbsd2 vih2 vil2 tbsy2 tsds2 sdtia vih2 vil2 tsdh2 tsyd2 figure 17. pcm i/f a timing at msb justified and i 2 s (slave mode) 1/fs2 50%tvdd2 synca tsyh2 tsyl2 dsyc2 = tsyl2 x fs2 x 100 tbck2 = 1/fbck2 tbckl2 50%tvdd2 tbckh2 bicka dbck2 = tbckl2 / tbck2 x 100 figure 18. clock timing of pcm i/f a (master mode)
[ak4671] ms0666-e-02 2010/06 - 34 - tsyb2 synca 50%tvdd2 bicka sdtoa 50%tvdd2 tbsd2 50%tvdd2 tsds2 sdtia vih2 vil2 tsdh2 50%tvdd2 bicka (bckpa = ?0?) (bckpa = ?1?) figure 19. pcm i/f a timing at short and long frame sync (master mode; msbsa = ?0?) tsyb2 synca 50%tvdd2 bicka sdtoa 50%tvdd2 tbsd2 50%tvdd2 tsds2 sdtia vih2 vil2 tsdh2 50%tvdd2 bicka (bckpa = ?1?) (bckpa = ?0?) figure 20. pcm i/f a timing at short and long frame sync (master mode; msbsa = ?1?)
[ak4671] ms0666-e-02 2010/06 - 35 - synca 50%tvdd2 bicka sdtoa 50%tvdd2 tbsd2 50%tvdd2 tsds2 sdtia vih2 vil2 tsdh2 tsyd2 tmbsy2 figure 21. pcm i/f a timing at msb justified and i 2 s (master mode) 1/fs2 vih3 vil3 syncb tsyh3 tsyl3 dsyc3 = tsyh3 x fs2 x 100 tsyl3 x fs2 x 100 tbck3 = 1/fbck3 tbckl3 vih3 tbckh3 vil3 bickb figure 22. clock timing of pcm i/f b (slave mode)
[ak4671] ms0666-e-02 2010/06 - 36 - tsyb3 syncb vih3 bickb vil3 sdtob 50%tvdd3 tbsd3 vih3 vil3 tbsy3 tsds3 sdtib vih3 vil3 tsdh3 tsyd3 vih3 bickb vil3 (bckpb = ?0?) (bckpb = ?1?) figure 23. pcm i/f b timing at short and long frame sync (slave mode; msbsb = ?0?) tsyb3 syncb vih3 bickb vil3 sdtob 50%tvdd3 tbsd3 vih3 vil3 tbsy3 tsds3 sdtib vih3 vil3 tsdh3 vih3 bickb vil3 (bckpb = ?1?) (bckpb = ?0?) figure 24. pcm i/f b timing at short and long frame sync (slave mode; msbsb = ?1?)
[ak4671] ms0666-e-02 2010/06 - 37 - tsyb3 syncb vih3 bickb vil3 sdtob 50%tvdd3 tbsd3 vih3 vil3 tbsy3 tsds3 sdtib vih3 vil3 tsdh3 tsyd3 figure 25. pcm i/f b timing at msb justified and i 2 s (slave mode) 1/fs2 50%tvdd3 syncb tsyh3 tsyl3 dsyc3 = tsyl3 x fs2 x 100 tbck3 = 1/fbck3 tbckl3 50%tvdd3 tbckh3 bickb dbck3 = tbckl3 / tbck3 x 100 figure 26. clock timing of pcm i/f b (master mode)
[ak4671] ms0666-e-02 2010/06 - 38 - tsyb3 syncb 50%tvdd3 bickb sdtob 50%tvdd3 tbsd3 50%tvdd3 tsds3 sdtib vih3 vil3 tsdh3 50%tvdd3 bickb (bckpb = ?0?) (bckpb = ?1?) figure 27. pcm i/f b timing at short and long frame sync (master mode; msbsb = ?0?) tsyb3 syncb 50%tvdd3 bickb sdtob 50%tvdd3 tbsd3 50%tvdd3 tsds3 sdtib vih3 vil3 tsdh3 50%tvdd3 bickb (bckpb = ?1?) (bckpb = ?0?) figure 28. pcm i/f b timing at short and long frame sync (master mode; msbsb = ?1?)
[ak4671] ms0666-e-02 2010/06 - 39 - syncb 50%tvdd3 bickb sdtob 50%tvdd3 tbsd3 50%tvdd3 tsds3 sdtib vih3 vil3 tsdh3 tsyd3 tmbsy3 figure 29. pcm i/f b timing at msb justified and i 2 s (master mode) csn vih1 vil1 tcss cclk tcds vih1 vil1 cdti vih1 tcckh tcckl tcdh vil1 c1 c0 r/w tcck tcsh cdto hi-z figure 30. write command input timing
[ak4671] ms0666-e-02 2010/06 - 40 - csn vih1 vil1 tcsh cclk vih1 vil1 cdti vih1 tcsw vil1 d1 d0 d2 tcss cdto hi-z figure 31. write data input timing csn vih1 vil1 cclk vih1 vil1 cdti vih1 vil1 a0 cdto a1 50%dvdd tdcd d7 d6 hi-z figure 32. read data output timing 1
[ak4671] ms0666-e-02 2010/06 - 41 - csn vih1 vil1 tcsh cclk vih1 vil1 cdti vih1 tcsw vil1 cdto 50%dvdd d2 d1 d0 tccz hi-z figure 33. read data output timing 2 stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih1 vil1 thd:sta tsu:sta vih1 vil1 tsu:sto tsp figure 34. i 2 c bus mode timing
[ak4671] ms0666-e-02 2010/06 - 42 - pmadl bit or pmadr bit tpdv sdto 50%dvdd figure 35. power down & reset timing 1 tpd pdn vil1 figure 36. power down & reset timing 2 pmsra bit tpdv2 sdtoa 50%tvdd2 figure 37. power down & reset timing 3 pmsrb bit tpdv3 sdto 50%dvdd figure 38. power down & reset timing 4
[ak4671] ms0666-e-02 2010/06 - 43 - operation overview system clock (audio i/f) there are the following five clock modes to interface with external devices. ( table 1 and table 2 ) mode pmpll bit m/s bit pll3-0 bits figure pll master mode ( note 60 ) 1 1 see table 4 figure 39 pll slave mode 1 (pll reference clock: mcki pin) 1 0 see table 4 figure 40 pll slave mode 2 (pll reference clock: lrck or bick pin) 1 0 see table 4 figure 41 figure 42 ext slave mode 0 0 x figure 43 ext master mode 0 1 x figure 44 note 60. if m/s bit = ?1?, pmpll bit = ?0? and mcko bit = ?1? during the setting of pll master mode, the invalid clocks are output from mcko pin when mcko bit is ?1?. table 1. clock mode setting (x: don?t care) mode mcko bit mcko pin mcki pin bick pin lrck pin 0 l pll master mode 1 selected by ps1-0 bits selected by pll3-0 bits output (selected by bcko bit) output (1fs) 0 l pll slave mode (pll reference clock: mcki pin) 1 selected by ps1-0 bits selected by pll3-0 bits input ( 32fs) input (1fs) pll slave mode (pll reference clock: lrck or bick pin) 0 l gnd input (selected by pll3-0 bits) input (1fs) ext slave mode 0 l selected by fs1-0 bits input ( 32fs) input (1fs) ext master mode 0 l selected by fs1-0 bits output (selected by bcko bit) output (1fs) table 2. clock pins state in clock mode master mode/slave mode the m/s bit selects either master or sl ave mode. m/s bit = ?1? selects master m ode and ?0? selects slave mode. when the ak4671 is power-down mode (pdn pin = ?l?) and exits reset st ate, the ak4671 is slave mode. after exiting reset state, the ak4671 goes to master mode by changing m/s bit = ?1?. when the ak4671 is used by master mode, lrck and bick pi ns are a hi-z state until m/s bit becomes ?1?. lrck and bick pins of the ak4671 should be pulled-down or pulled-up by the resistor (about 100k ) externally to avoid the floating state. m/s bit mode 0 slave mode (default) 1 master mode table 3. select master/slave mode
[ak4671] ms0666-e-02 2010/06 - 44 - pll mode (pmpll bit = ?1?) when pmpll bit is ?1?, a fully integrated analog phase lock ed loop (pll) generates a clock that is selected by the pll3-0 and fs3-0 bits. the pll lock time is shown in table 4 , whenever the ak4671 is supplied to a stable clocks after pll is powered-up (pmpll bit = ?0? ?1?) or sampling frequency changes. when ain3 bit = ?1?, the pll is not available. 1) setting of pll mode r and c of vcoc pin mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency r[ ] c[f] pll lock time (max) 0 0 0 0 0 lrck pin 1fs 6.8k 220n 160ms 10k 4.7n 2ms 2 0 0 1 0 bick pin 32fs 10k 10n 4ms 10k 4.7n 2ms 3 0 0 1 1 bick pin 64fs 10k 10n 4ms 4 0 1 0 0 mcki pin 11.2896mhz 10k 4.7n 40ms 5 0 1 0 1 mcki pin 12.288mhz 10k 4.7n 40ms 6 0 1 1 0 mcki pin 12mhz 10k 10n 40ms (default) 7 0 1 1 1 mcki pin 24mhz 10k 10n 40ms 8 1 0 0 0 mcki pin 19.2mhz 10k 4.7n 40ms 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 40ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 40ms 14 1 1 1 0 mcki pin 13mhz 10k 220n 60ms 15 1 1 1 1 mcki pin 26mhz 10k 220n 60ms others others n/a table 4. setting of pll mode (*fs: sampling frequency, n/a: not available) 2) setting of sampling frequency in pll mode when pll reference clock input is mcki pin, the sampli ng frequency is selected by fs3-0 bits as defined in table 5 . mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 5 0 1 0 1 11.025khz 7 0 1 1 1 22.05khz 10 1 0 1 0 32khz 11 1 0 1 1 48khz 15 1 1 1 1 44.1khz (default) others others n/a (n/a: not available) table 5. setting of sampling frequency at pmpll bit = ?1? (reference clock = mcki pin)
[ak4671] ms0666-e-02 2010/06 - 45 - when pll reference clock input is lrck or bick pin, the sampling frequency is selected by fs3-2 bits ( table 6 ). mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 0 x x 8khz fs 12khz 1 0 1 x x 12khz < fs 24khz 2 1 x x x 24khz < fs 48khz (default) others others n/a (x: don?t care, n/a: not available) table 6. setting of sampling frequency at pmpll bit = ?1? (reference clock = lrck or bick pin) pll unlock state 1) pll master mode (pmpll bit = ?1?, m/s bit = ?1?) in this mode, lrck and bick pins go to ?l? and irregul ar frequency clock is output from the mcko pin at mcko bit is ?1? before the pll goes to lo ck state after pmpll bit = ?0? ? ?1?. if mcko bit is ?0?, the mcko pin changes to ?l? ( table 7 ). after the pll is locked, a first period of lrck and bick may be invalid clock, but these clocks return to normal state after a period of 1/fs. when sampling frequency is changed, bick and lrck pins do not output irregular frequency clocks but go to ?l? by setting pmpll bit to ?0?. mcko pin pll state mcko bit = ?0? mcko bit = ?1? bick pin lrck pin after that pmpll bit ?0? ? ?1? ?l? output invalid ?l? output ?l? output pll unlock (except above case) ?l? output invalid invalid invalid pll lock ?l? output see table 9 see table 10 1fs output table 7. clock operation at pll master mode (pmpll bit = ?1?, m/s bit = ?1?) 2) pll slave mode (pmpll b it = ?1?, m/s bit = ?0?) in this mode, an invalid clock is output from the mcko pin before the pll goes to lock state after pmpll bit = ?0? ? ?1?. after that, the clock selected by table 9 is output from the mcko pin when pll is locked. adc and dac output invalid data when the pll is unlocked. for dac, the out put signal should be muted by writing ?0? to dacl and dach bits. mcko pin pll state mcko bit = ?0? mcko bit = ?1? after that pmpll bit ?0? ? ?1? ?l? output invalid pll unlock ?l? output invalid pll lock ?l? output output table 8. clock operation at pll slave mode (pmpll bit = ?0?, m/s bit = ?0?)
[ak4671] ms0666-e-02 2010/06 - 46 - pll master mode (pmpll bit = ?1?, m/s bit = ?1?) when an external clock (11.2896mhz, 12mhz, 12.288mhz , 13mhz, 13.5mhz, 19.2mhz, 24mhz, 26mhz or 27mhz) is input to the mcki pin, the mcko, bick and lrck clocks are generated by an internal pll circuit. the mcko output frequency is selected by ps1-0 bits ( table 9 ) and the output is enabled by mcko bit. the bick output frequency is selected between 32fs or 64fs, by bcko bit ( table 10 ). a k4671 dsp or p mcko bick lrck sdto sdti bclk lrck sdti sdto mcki 1fs 32fs, 64fs 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 12.288mhz, 13mhz, 13.5mhz, 19.2mhz, 24mhz, 26mhz, 27mhz mclk figure 39. pll master mode mode ps1 bit ps0 bit mcko pin 0 0 0 256fs (default) 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 9. mcko output frequency (pll mode, mcko bit = ?1?) bcko bit bick output frequency 0 32fs (default) 1 64fs table 10. bick output frequency at master mode
[ak4671] ms0666-e-02 2010/06 - 47 - pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to mcki, bick or lrck pin. the required clock to the ak4671 is generated by an internal pll circuit. input frequency is selected by pll3-0 bits ( table 4 ). a) pll reference clock: mcki pin bick and lrck inputs should be synchronized with mcko output. the phase between mcko and lrck does not matter. the mcko pin outputs the frequency selected by ps1-0 bits ( table 9 ) and the output is enabled by mcko bit. sampling frequency can be selected by fs3-0 bits ( table 5 ). in case that the codec is used without audio i/f (like phone call), the codec can be operated by mcki only. in this case, bick and lrck can be stopped. a k4671 dsp or p mcko bick lrck sdto sdti bclk lrck sdti sdto mcki 1fs 32fs mclk 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 12.288mhz, 13mhz, 13.5mhz, 19.2mhz, 24mhz, 26mhz, 27mhz figure 40. pll slave mode 1 (pll reference clock: mcki pin)
[ak4671] ms0666-e-02 2010/06 - 48 - b) pll reference clock: bick or lrck pin sampling frequency corresponds to 8khz to 48khz by changing fs3-0 bits ( table 6 ). a k4671 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs or 64fs figure 41. pll slave mode 2 (pll reference clock: bick pin) a k4671 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs figure 42. pll slave mode 2 (pll reference clock: lrck pin) mcki should always be present whenever the adc or dac is in operation (pmadl bit = ?1?, pmadr bit = ?1?, pmdal bit = ?1? or pmdar bit = ?1?). if mcki is not provided, the ak4671 may draw excess current and it is not possible to operate properly because utili zes dynamic refreshed logic internally. if mcki is not present, the adc and dac should be in the power-down mode (pmadl=pmadr=pmdal=pmdar bits = ?0?).
[ak4671] ms0666-e-02 2010/06 - 49 - ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) when pmpll bit is ?0?, the ak4671 becomes ext mode. master clock is input from the mcki pin, the internal pll circuit is not operated. this mode is compatible with i/f of the normal audio codec. the clocks required to operate the ak4671 are mcki (256fs, 384fs, 512fs, 768fs or 1024fs), lrck (fs) and bick ( 32fs). the master clock (mcki) should be synchronized with lrck. the phase between these clocks does not matter. the input frequency of mcki is selected by fs2-0 bits ( table 11 ). in case that the codec is used without audio i/f (like phone call), the codec can be operated by mcki only. in this case, bick and lrck can be stopped. mode fs3 bit fs2 b it fs1 bit fs0 bit mcki input frequency sampling frequency range 0 x 0 0 0 256fs 8khz 48khz 1 x 0 0 1 1024fs 8khz 13khz 4 x 1 0 0 384fs 8khz 48khz 5 x 1 0 1 768fs 8khz 26khz 6 x 1 1 0 512fs 8khz 26khz 7 x 1 1 1 256fs 8khz 48khz (default) others others n/a n/a (x: don?t care, n/a: not available) table 11. mcki frequency at ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be reduced by using higher frequenc y of the master clock. the s/n of the dac output through lout/rout pins at fs=8khz is shown in table 12 . mcki s/n (fs=8khz, 20khzlpf + a-weighted) 256fs, 384fs 83db 512fs, 768fs 93db 1024fs 93db table 12. relationship between mcki and s/n of lout1/rout1 pins mcki should always be present whenever the adc or dac is in operation (pmadl bit = ?1?, pmadr bit = ?1?, pmdal bit = ?1? or pmdar bit = ?1?). if mcki is not provided, the ak4671 may draw excess current and it is not possible to operate properly because utili zes dynamic refreshed logic internally. if mcki is not present, the adc and dac should be in the power-down mode (pmadl=pmadr=pmdal=pmdar bits = ?0?). a k4671 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs mclk 256fs, 384fs, 512fs, 768fs or 1024fs figure 43. ext slave mode
[ak4671] ms0666-e-02 2010/06 - 50 - ext master mode (pmpll bit = ?0?, m/s bit = ?1?) the ak4671 becomes ext master mode by setting pmpll bit = ?0? and m/s bit = ?1?. master clock is input from the mcki pin, the internal pll circuit is not operated. the clock required to operate is mcki (256fs, 384fs, 512fs, 768fs or 1024fs). the input frequency of mcki is selected by fs2-0 bits ( table 13 ). mode fs3 bit fs2 b it fs1 bit fs0 bit mcki input frequency sampling frequency range 0 x 0 0 0 256fs 8khz 48khz 1 x 0 0 1 1024fs 8khz 13khz 4 x 1 0 0 384fs 8khz 48khz 5 x 1 0 1 768fs 8khz 26khz 6 x 1 1 0 512fs 8khz 26khz 7 x 1 1 1 256fs 8khz 48khz (default) others others n/a n/a (x: don?t care, n/a: not available) table 13. mcki frequency at ext master mode (pmpll bit = ?0?, m/s bit = ?1?) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be reduced by using higher frequenc y of the master clock. the s/n of the dac output through lout/rout pins at fs=8khz is shown in table 14 . mcki s/n (fs=8khz, 20khzlpf + a-weighted) 256fs, 384fs 83db 512fs, 768fs 93db 1024fs 93db table 14. relationship between mcki and s/n of lout1/rout1 pins mcki should always be present whenever the adc or dac is in operation (pmadl bit = ?1?, pmadr bit = ?1?, pmdal bit = ?1? or pmdar bit = ?1?). if mcki is not provided, the ak4671 may draw excess current and it is not possible to operate properly because utili zes dynamic refreshed logic internally. if mcki is not present, the adc and dac should be in the power-down mode (pmadl=pmadr=pmdal=pmdar bits = ?0?). a k4671 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs or 64fs mclk 256fs, 384fs, 512fs, 768fs or 1024fs figure 44. ext master mode bcko bit bick output frequency 0 32fs (default) 1 64fs table 15. bick output frequency at master mode
[ak4671] ms0666-e-02 2010/06 - 51 - system reset when power-up, the ak4671 should be reset by bringing the pdn pi n = ?l?. this ensures that all internal registers reset to their initial values. the adc enters an initialization cycle that starts when th e pmadl or pmadr bit is changed from ?0? to ?1? at pmdal and pmdar bits are ?0?. the initialization cycle time is 1059/fs=24ms@fs=44.1khz. during the initialization cycle, the adc digital data outputs of both channels are forced to a 2?s complement, ?0?. the adc output reflects the analog input signal after the initialization cycle is complete. when pmdal or pmdar is ?1?, the adc does not require an initialization cycle. audio interface format four types of data formats are available and can be selected by setting the dif1-0 bits ( table 16 ). in all modes, the serial data is msb first, 2?s complement format. audio interface fo rmats can be used in both master and slave modes. lrck and bick are output from the ak4671 in master mode, but must be input to the ak4671 in slave mode. mode dif1 bit dif0 bit sdto (adc) sdti (dac) bick figure 0 0 0 dsp mode dsp mode 32fs table 17 1 0 1 msb justified lsb justified 32fs figure 49 2 1 0 msb justified msb justified 32fs figure 50 (default) 3 1 1 i 2 s compatible i 2 s compatible 32fs figure 51 table 16. audio interface format in modes 1, 2 and 3, the sdto is clocked out on the falling edge (? ?) of bick and the sdti is latched on the rising edge (? ?). in modes 0 (dsp mode), the audio i/f timing is changed by bckp and msbs bits ( table 17 ). dif1 dif0 msbs bckp audio interface format figure 0 0 msb of sdto is output by the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. msb of sdti is latched by the falling edge (? ?) of the bick just after the output timing of sdto?s msb. figure 45 (default) 0 1 msb of sdto is output by the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. msb of sdti is latched by the rising edge (? ?) of the bick just after the output timing of sdto?s msb. figure 46 1 0 msb of sdto is output by next rising edge (? ?) of the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. msb of sdti is latched by the falling edge (? ?) of the bick just after the output timing of sdto?s msb. figure 47 0 0 1 1 msb of sdto is output by next falling edge (? ?) of the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. msb of sdti is latched by the rising edge (? ?) of the bick just after the output timing of sdto?s msb. figure 48 table 17. audio interface format in mode 0 if 16-bit data that adc outputs is converted to 8-bit data by removing lsb 8-bit, ? ? 1? at 16bit data is converted to ? ? 1? at 8-bit data. and when the dac playbacks this 8-bit data, ? ? 1? at 8-bit data will be converted to ? ? 256? at 16-bit data and this is a large offset. this offset can be removed by addi ng the offset of ?128? to 16-bit data before converting to 8-bit data.
[ak4671] ms0666-e-02 2010/06 - 52 - lrck bick ( 32fs ) sdto(o) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 0 15 5 8 7 1 43 10 13 2 6 0 15 5 87 1 4 3 2 6 29 26 0 2 14 14 18 bick ( 64fs ) sdto(o) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 15 2 1 16 0 15 21 0 48 15:msb, 0:lsb 1/fs 2 14 14 34 lch lch rch rch sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 lch rch sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck (master) (slave) figure 45. mode 0 timing (bckp = ?0?, msbs = ?0?) rch lch bick ( 32fs ) sdto(o) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 0 15 5 8 7 1 43 10 13 2 6 0 15 5 87 1 4 3 2 6 29 26 0 2 14 14 18 bick ( 64fs ) sdto(o) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 15 2 1 16 0 15 21 0 48 15:msb, 0:lsb 1/fs 2 14 14 34 lch rch sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 lch rch sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck lrck (master) (slave) figure 46. mode 0 timing (bckp = ?1?, msbs = ?0?)
[ak4671] ms0666-e-02 2010/06 - 53 - bick ( 32fs ) sdto(o) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 0 15 5 8 7 1 43 10 13 2 6 0 15 5 87 1 4 3 2 6 29 26 0 2 14 14 18 bick ( 64fs ) sdto(o) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 15 2 1 16 0 15 21 0 48 15:msb, 0:lsb 1/fs 2 14 14 34 lch lch rch rch sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 lch rch sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck lrck (master) (slave) figure 47. mode 0 timing (bckp = ?0?, msbs = ?1?) rch lch bick ( 32fs ) sdto(o) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 0 15 5 8 7 1 43 10 13 2 6 0 15 5 87 1 4 3 2 6 29 26 0 2 14 14 18 bick ( 64fs ) sdto(o) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 15 2 1 16 0 15 21 0 48 15:msb, 0:lsb 1/fs 2 14 14 34 lch rch sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 lch rch sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck lrck (master) (slave) figure 48. mode 0 timing (bckp = ?1?, msbs = ?1?)
[ak4671] ms0666-e-02 2010/06 - 54 - lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 13 13 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 13 1 0 15 15 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 10 1 15 15 210 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 15 14 13 76543 10 2 15 14 13 10 figure 49. mode 1 timing lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 13 13 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 13 1 0 15 15 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 1 15 15 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 13 10 13 10 15 15 14 13 76543 10 2 15 14 13 10 figure 50. mode 2 timing
[ak4671] ms0666-e-02 2010/06 - 55 - lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 1 0 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 don't care 2 15 1 15 15 15 don't care 15:msb, 0:lsb lch data rch data 14 21 14 21 8 8 8 0 0 0 0 0 15 14 76543 210 8 15 14 21 0 figure 51. mode 3 timing
[ak4671] ms0666-e-02 2010/06 - 56 - mic/line input selector the ak4671 has input selector. when mdif1, mdif2, mdif3 and mdif4 bits are ?0?, inl1-0 and inr1-0 bits select lin1/lin2/lin3/lin4 and rin1/rin2/rin3/rin4, respectively. when mdif1, mdif2, mdif3 and mdif4 bits are ?1?, lin1/rin1, lin2/rin2, lin3/rin3 and lin4/rin4 pins become in1+/ ? , in2+/ ? , in3+/ ? and in4+/ ? pins, respectively. in this case, full-differential input is available ( figure 53 ). mdif1 mdif2 mdif3 mdif4 inl1 inl0 inr1 inr0 lch rch 0 0 0 0 0 0 0 0 lin1 rin1 (default) 0 0 0 0 0 0 0 1 lin1 rin2 0 0 0 0 0 0 1 0 lin1 rin3 0 0 0 0 0 0 1 1 lin1 rin4 0 0 0 0 0 1 0 0 lin2 rin1 0 0 0 0 0 1 0 1 lin2 rin2 0 0 0 0 0 1 1 0 lin2 rin3 0 0 0 0 0 1 1 1 lin2 rin4 0 0 0 0 1 0 0 0 lin3 rin1 0 0 0 0 1 0 0 1 lin3 rin2 0 0 0 0 1 0 1 0 lin3 rin3 0 0 0 0 1 0 1 1 lin3 rin4 0 0 0 0 1 1 0 0 lin4 rin1 0 0 0 0 1 1 0 1 lin4 rin2 0 0 0 0 1 1 1 0 lin4 rin3 0 0 0 0 1 1 1 1 lin4 rin4 0 0 0 1 0 0 1 1 lin1 in4+/ ? 0 0 0 1 0 1 1 1 lin2 in4+/ ? 0 0 0 1 1 0 1 1 lin3 in4+/ ? 0 0 1 0 1 0 0 0 in3+/ ? rin1 0 0 1 0 1 0 0 1 in3+/ ? rin2 0 0 1 0 1 0 1 1 in3+/ ? rin4 0 0 1 1 1 0 1 1 in3+/ ? in4+/ ? 0 1 0 0 0 0 0 1 lin1 in2+/ ? 0 1 0 0 1 0 0 1 lin3 in2+/ ? 0 1 0 0 1 1 0 1 lin4 in2+/ ? 0 1 1 0 1 0 0 1 in3+/ ? in2+/ ? 1 0 0 0 0 0 0 1 in1+/ ? rin2 1 0 0 0 0 0 1 0 in1+/ ? rin3 1 0 0 0 0 0 1 1 in1+/ ? rin4 1 0 0 1 0 0 1 1 in1+/ ? in4+/ ? 1 1 0 0 0 0 0 1 in1+/ ? in2+/ ? others n/a table 18. mic-amp input signal (n/a: not available)
[ak4671] ms0666-e-02 2010/06 - 57 - lin1/in1+ pin a dc lch rin1/in1 ? pin inl1-0 bits mdif1 bit mdif3 bit lin2/in2+ pin a dc rch rin2/in2 ? pin inr1-0 bits mdif2 bit mdif4 bit ak4671 lin3/in3+ pin rin3/in3 ? pin lineout mic-amp lch mic-amp rch pmainl3 bit pmainr3 bit pmainl2 bit pmainr2 bit pmainl1 bit pmainr1 bit lin4/in4+ pin rin4/in4 ? pin pmloopl bit pmloopr bit pmainl4 bit pmainr4 bit figure 52. mic/line input selector in1+ pin in1 ? pin mpwr pin a k4671 mic-amp 1k 1k figure 53. connection example for full-differential mic input (mdif1/2/3/4 bits = ?1?) in1+ pin in1 ? pin a k4671 mic-amp figure 54. connection example for full-differential mic input (mdif1/2/3/4 bits = ?1?)
[ak4671] ms0666-e-02 2010/06 - 58 - mic gain amplifier the ak4671 has a gain amplifier for microphone input. the gain of mic-amp lch and rch is independently selected by the mgnl3-0 and mgnr3-0 bits ( table 19 ). the typical input impedance is 42k (typ)@mgnl/r0 bits = ?0? or 30k (typ)@mgnl/r0 bits = ?1?. mode mgnl3 mgnr3 mgnl2 mgnr2 mgnl1 mgnr1 mgnl0 mgnr0 input gain input resistance 0 0 0 0 0 n/a n/a 1 0 0 0 1 ? 12db 30k 2 0 0 1 0 ? 9db 42k 3 0 0 1 1 ? 6db 30k 4 0 1 0 0 ? 3db 42k 5 0 1 0 1 0db 30k (default) 6 0 1 1 0 +3db 42k 7 0 1 1 1 +6db 30k 8 1 0 0 0 +9db 42k 9 1 0 0 1 +12db 30k 10 1 0 1 0 +15db 42k 11 1 0 1 1 +18db 30k 12 1 1 0 0 +21db 42k 13 1 1 0 1 +24db 30k 14 1 1 1 0 +27db 42k 15 1 1 1 1 +30db 30k table 19. mic input gain (n/a: not available)
[ak4671] ms0666-e-02 2010/06 - 59 - mic power when pmmp bit = ?1?, the mpwr pin supplies power for the microphone. this output voltage is typically 0.8 x avdd and the load resistance is minimum 0.5k . in case of using two sets of stereo mic, the load resistance is minimum 2k for each channel. any capacitor must not be connected directly to the mpwr pin ( figure 55 ). pmmp bit mpwr pin 0 hi-z (default) 1 output table 20. mic power mpwr pin figure 55. mic block circuit
[ak4671] ms0666-e-02 2010/06 - 60 - mic detection the ak4671 has the detecting function of microphone . the external circuit is showed in figure 56 . the followings show the example of ex ternal microphone detection sequence: (1) pmmp bit should be set to ?1? after cpu det ects the jack insertion of microphone or headphone. (2) the mpwr pin drives external microphone. (3) the gpo2 pin (at gpom2 bit = ?1 ?) and dtmic bit are set as table 21 . in case of headset (with mic), the input voltage of mdt pin is higher than 0.075 x avdd because of the relationship between the bias resistance at the mpwr pin (typ. 2.2k ) and the microphone impedance. in case of h eadphone (no mic), the input voltage of mdt pin is 0v because the pin of headphone jack c onnected to the mdt pin is assigned as ground. input level of mdt pin gpo2 pin dtmic bit result 0.075 x avdd h 1 mic (headset) < 0.050 x avdd l 0 no mic (headphone) table 21. microphone detection result lin1 lin2 mpwr dtmic bit mdt 0.075 x avdd pmmp bit typ. 500k g m r l headset g r l headphone or ak4671 figure 56. microphone power supply and mic detection
[ak4671] ms0666-e-02 2010/06 - 61 - digital block digital block is composed as figure 57 . each block can be powered-down by power management bits (pmadl, pmadr, pmdal, pmdar, pmsra, pmsrb and pmpcm bits). when blocks from hpf to mix are powered-down, both mix and svola blocks shoul d not be selected by sdol/r bits and pfmxl/r bits. sdto lch sdti lch sdtoa sdtia sdtob sdtib pmsra pmsrb a/d stereo separation pmadl or pmadr d/a m i x pmdal or pmdar or pmsra alc 5-band notch datt smute pfsel=0 pmadl or pmadr pfsel=1 pmdal or pmdar or pmsra lpf hpf src-a src-b datt-c datt-b svolb hpf mix svola 5-band eq s e l bivol sdto rch sdti rch pfsel a dm sdol/r1-0 sdod srmxl/r1-0 sdim1-0 pfmxl/r1-0 sdoa sdoad sbmx1-0 bvmx1-0 dam, mixd sra1-0, mixd hpfad hpf lpf fil3, eq0, gn1-0 eq1-5 a lc, ivl/r sval/r2-0 sdobd ovl/r eq svb2-0 bvl7-0 cvl7-0 biv2-0 pmpcm pmdal or pmdar figure 57. path select of digital block
[ak4671] ms0666-e-02 2010/06 - 62 - 1. adc: include the digital filter (lpf) for adc as shown in ? filter chracteristics ?. 2. dac: include the digital filter (lpf) for dac as shown in ? filter chracteristics ?. 3. hpf: high pass filter. applicable to use as wind-noise reduction filter. (see ? digital programmable filter ?.) 4. lpf: low pass filter (see ? digital programmable filter ?.) 5. stereo separation: stereo separation emphasis filter & gain compensation. (see ? digital programmable filter ?.) gain compensation is composed with eq0 and gain blocks . this block adjusts the fre quency response after stereo separation emphasis. 6. 5-band notch: applicable to use as equalizer or notch filter. (see ? digital programmable filter ?.) 7. alc: input digital volume with alc function. (see ? input digital volume ? and ? alc operation ?.) 8. svola: side tone volume at internal mic/ spk or external headset phone call. (see ? side tone volume ?.) 9. 5-band eq: equalizer for playback path. (see ? 5-band equalizer ?.) 10. datt: digital volume for playback path. (see ? digital output volume ?.) 11. smute: soft mute. (see ? soft mute ?.) 12. datt-b: digital volume for reco rding of received voice. (see ? digital volume for recording of received voice ?) 13. datt-c: digital volume of received voice. (see ? digital volume for received voice ?) 14. svola: side tone volume at b/t headset phone call. (see ? side tone volume for b/t phone call ?.) mode pmadl pmadr pm dal pmdar pfsel figure recording mode 1 1 0 0 0 1 0 0 0 0 figure 58 0 1 0 0 0 recording & 1 1 1 1 0 playback mode 1 0 1 1 0 figure 59 0 1 1 1 0 playback mode 0 0 1 1 1 figure 60 table 22. recode/playback mode 2nd order hpf adc 5 band notch alc (volume) 1st order lpf stereo separation gain compensation figure 58. path at recording mode dac 2nd order hpf adc 5 band notch alc (volume) smute dem 1st order lpf stereo separation gain compensation datt 5 band eq figure 59. path at recording & playback mode dac 1st order hpf adc 5 band eq alc (volume) 1st order lpf stereo separation gain compensation 1st order hpf ?0? data smute dem datt 5 band eq figure 60. path at playback mode
[ak4671] ms0666-e-02 2010/06 - 63 - digital programmable filter (1) high pass filter (hpf) normally, this hpf is used for a wind-noise reduction filter. this is composed of 2 steps of 1st order hpf. the coefficient of both hpf is the same and set by f1a13-0 b its and f1b13-0 bits. hpfad bit controls on/off of the 1st step hpf and hpf bit controls on/off of the 2nd step hpf. wh en the hpf is off, the audio data passes this block by 0db gain. the coefficient should be set when hpfad= hpf bits = ?0? or pmadl=pmadr=pmdal=pmdar bits = ?0?. fs: sampling frequency fc: cut-off frequency register setting ( note 61 ) hpf: f1a[13:0] bits =a, f1b[13:0] bits =b (msb=f1a13, f1b13; lsb=f1a0, f1b0) a = 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 ? z ? 1 1 + bz ? 1 the cut-off frequency should be set as below. fc/fs 0.0001 (fc min = 4.41hz at 44.1khz) (2) low pass filter (lpf) this is composed with 1st order lpf. f2a13-0 bits and f2b 13-0 bits set the coefficient of lpf. lpf bit controls on/off of the lpf. when the lpf is off, the audio data passes this block by 0db gain. the coeffi cient should be set when lpf bit = ?0? or pmadl=pmadr=pmdal=pmdar bits = ?0?. fs: sampling frequency fc: cut-off frequency register setting ( note 61 ) lpf: f2a[13:0] bits =a, f2b[13:0] bits =b (msb=f2a13, f1b13; lsb=f2a0, f2b0) a = 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 + z ? 1 1 + bz ? 1 the cut-off frequency should be set as below. fc/fs 0.05 (fc min = 2205hz at 44.1khz)
[ak4671] ms0666-e-02 2010/06 - 64 - (3) stereo separation emphasis filter (fil3) fil3 is used to emphasize the stereo sepa ration of stereo mic recording data or playback data. f3a13-0 and f3b13-0 bits set the filter coefficient of fil3. fil3 becomes high pass filter (hpf) at f3as bit = ?0?, and low pass filter (lpf) at f3as bit = ?1?. fil3 bit controls on/ off of fil3. when stereo separation em phasis filter is off, the audio data passes this block by 0db gain. the co efficient should be set when fil3 bit = ?0? or pmadl = pmadr = pmdal = pmdar bits = ?0?. 1) when fil3 is set to ?hpf? fs: sampling frequency fc: cut-off frequency k: filter gain [db] (0db k ? 10db) register setting ( note 61 ) fil3: f3as bit = ?0?, f3a[13:0] bits =a, f3b[13:0] bits =b (msb=f3a13, f3b13; lsb=f3a0, f3b0) a = 10 k/20 x 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 ? z ? 1 1 + bz ? 1 2) when fil3 is set to ?lpf? fs: sampling frequency fc: cut-off frequency k: filter gain [db] (0db k ? 10db) register setting ( note 61 ) fil3: f3as bit = ?1?, f3a[13:0] bits =a, f3b[13:0] bits =b (msb=f3a13, f3b13; lsb= f3a0, f3b0) a = 10 k/20 x 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 + z ? 1 1 + bz ? 1
[ak4671] ms0666-e-02 2010/06 - 65 - (4) gain compensation (eq0) gain compensation is used to compensate the frequency res ponse and the gain that is ch anged by stereo separation emphasis filter. gain compensation is composed with e qualizer (eq0) and the gain (0db/+12db/+24db). e0a15-0, e0b13-0 and e0c15-0 bits set the coeffici ent of eq0. gn1-0 bits set the gain ( table 23 ). eq0 bit controls on/off of eq0. when eq is off and the gain is 0db, the audio data passes this block by 0db gain. the coefficient should be set when eq0 bit = ?0? or pmadl=pmadr=pmdal=pmdar bits = ?0?. fs: sampling frequency fc 1 : pole frequency fc 2 : zero-point frequency k: filter gain [db] (maximum +12db) register setting ( note 61 ) e0a[15:0] bits =a, e0b[13:0] bits =b, e0c[15:0] bits =c (msb=e0a15, e0b13, e0c15; lsb=e0a0, e0b0, e0c0) a = 10 k/20 x 1 + 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) b = 1 ? 1 / tan ( fc 1 /fs) 1 + 1 / tan ( fc 1 /fs) , c =10 k/20 x 1 ? 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) , transfer function h(z) = a + cz ? 1 1 + bz ? 1 gain[db] k fc 1 fc 2 frequency figure 61. eq0 frequency response gn1 gn0 gain 0 0 0db (default) 0 1 +12db 1 x +24db table 23. gain select of gain block (x: don?t care)
[ak4671] ms0666-e-02 2010/06 - 66 - (5) 5-band notch this block can be used as equalizer or notch filter. 5-band equalizer (eq1, eq2, eq3, eq4 and eq5) is on/off independently by eq1, eq2, eq3, eq4 and eq5 bits. when e qualizer is off, the audio da ta passes this block by 0db gain. e1a15-0, e1b15-0 and e1c15-0 bits set the coeffici ent of eq1. e2a15-0, e2b15-0 and e2c15-0 bits set the coefficient of eq2. e3a15-0, e3b15-0 and e3c15-0 bits se t the coefficient of eq3. e4a15-0, e4b15-0 and e4c15-0 bits set the coefficient of eq4. e5a15-0, e5b15-0 and e5c15-0 bits set the coeffi cient of eq5. the eqx (x=1 5) coefficient should be set when eqx bit = ? 0 ? or pmadl=pmadr=pmdal=pmdar bits = ?0?. fs: sampling frequency fo 1 ~ fo 5 : center frequency fb 1 ~ fb 5 : band width where the gain is 3db different from center frequency k 1 ~ k 5 : gain ( ? 1 k n 3) register setting ( note 61 ) eq1: e1a[15:0] bits =a 1 , e1b[15:0] bits =b 1 , e1c[15:0] bits =c 1 eq2: e2a[15:0] bits =a 2 , e2b[15:0] bits =b 2 , e2c[15:0] bits =c 2 eq3: e3a[15:0] bits =a 3 , e3b[15:0] bits =b 3 , e3c[15:0] bits =c 3 eq4: e4a[15:0] bits =a 4 , e4b[15:0] bits =b 4 , e4c[15:0] bits =c 4 eq5: e5a[15:0] bits =a 5 , e5b[15:0] bits =b 5 , e5c[15:0] bits =c 5 (msb=e1a15, e1b15, e1c15, e2a15, e2b15, e2c15, e3a15, e3b15, e3c15, e4a15, e4b15, e4c15, e5a15, e5b15, e5c15; lsb= e1a0, e1b0, e1c0, e2a0, e2b0, e2c0, e3a0, e3b0, e3c0, e4a0, e4b0, e4c0, e5a0, e5b0, e5c0) a n = k n x tan ( fb n /fs) 1 + tan ( fb n /fs) b n = cos(2 fo n /fs) x 2 1 + tan ( fb n /fs) , c n = 1 ? tan ( fb n /fs) 1 + tan ( fb n /fs) , (n = 1, 2, 3, 4, 5) transfer function h n (z) = a n 1 ? z ? 2 1 ? b n z ? 1 ? c n z ? 2 h(z) = 1 + h 1 (z) + h 2 (z) + h 3 (z) + h 4 (z) + h 5 (z) (n = 1, 2, 3, 4, 5) the center frequency should be set as below. fo n / fs < 0.497 note 61. [translation the filter coeffici ent calculated by the equations above fro m real number to binary code (2?s complement)] x = (real number of filter coefficient calculated by the equations above) x 2 13 x should be rounded to integer, a nd then should be translated to binary code (2?s complement). msb of each filter coefficient se tting register is sine bit.
[ak4671] ms0666-e-02 2010/06 - 67 - alc operation the alc (automatic level control) is executed by alc bloc k when alc bit is ?1?. alc circuit operates at playback path for playback mode and operates at reco rding path for recording mode as shown in figure 60 . 1. alc limiter operation during the alc limiter operation, when either lch or rch exceeds the alc limiter detection level ( table 24 ), the ivl and ivr values (same value) are attenuated automatically by the amount defined by the alc limiter att step ( table 25 ). when zelmn bit = ?0? (zero cross detec tion is enabled), the ivl and ivr valu es are changed by alc limiter operation at the individual zero crossing points of lch and rch or at the zero crossi ng timeout. ztm1-0 bits set the zero crossing timeout period of both alc lim iter and recovery operation ( table 26 ). ivl and ivr values are attenuated 1 step immediately (period: 1/fs) by alc limite r operation when output level is over fs (digital full scale). when output level is not over fs, the ivl and ivr values are changed at the individual zero crossing points of lch and rch or at the zero crossing timeout. when zelmn bit = ?1? (zero cross detection is disabled), ivl and ivr values are immediately (period: 1/fs) changed by alc limiter operation. attenuation step is fixed to 1 step regardless of the setting of lmat1-0 bits. the attenuation operation is done continuously until the i nput signal level becomes alc limiter detection level ( table 24 ) or less. after completing the attenuate ope ration, unless alc bit is changed to ?0 ?, the operation repeats when the input signal level exceeds lmth1-0 bits. lmth1 lmth0 alc limier detection level alc recovery waiting counter reset level 0 0 alc output ? 2.5dbfs ? 2.5dbfs > alc output ? 4.1dbfs (default) 0 1 alc output ? 4.1dbfs ? 4.1dbfs > alc output ? 6.0dbfs 1 0 alc output ? 6.0dbfs ? 6.0dbfs > alc output ? 8.5dbfs 1 1 alc output ? 8.5dbfs ? 8.5dbfs > alc output ? 12dbfs table 24. alc limiter detection leve l / recovery counter reset level alc limiter att step lmat1 lmat0 alc output lmth alc output fs alc output fs + 6db alc output fs + 12db 0 0 1 1 1 1 (default) 0 1 2 2 2 2 1 0 2 4 4 8 1 1 1 2 4 8 table 25. alc limiter att step zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms (default) 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 26. alc zero cr ossing timeout period
[ak4671] ms0666-e-02 2010/06 - 68 - 2. alc recovery operation the alc recovery operation waits for the wtm2-0 bits ( table 27 ) to be set after completing the alc limiter operation. if the input signal does not exceed ?alc r ecovery waiting counter reset level? ( table 24 ) during the wait time, the alc recovery operation is executed. the ivl and ivr values are automatically incremen ted by rgain1-0 bits ( table 28 ) up to the set reference level ( table 29 ) with zero crossing detection which tim eout period is set by ztm1-0 bits ( table 26 ). then the ivl and ivr are set to the same value for both channels. the alc recove ry operation is executed in a period set by wtm2-0 bits. when zero cross is detected at both ch annels during the wait period set by wtm2-0 bits, the alc recovery operation waits until wtm2-0 pe riod and the next recovery operation is executed. if ztm1-0 is longer than wtm2-0 and no zero crossing occurs, the alc recovery operation is executed in a period set by ztm1-0 bits. for example, when the current ivl and ivr values are 30h a nd rgain1-0 bits are set to ?01?, ivl and ivr values are changed to 32h by the auto limiter operation and then the i nput signal level is gained by 0.75db (=0.375db x 2). when the ivl and ivr values exceed the reference level (ref 7-0 bits), the ivl and ivr values are not increased. when ?alc recovery waiting counter reset level (lmth1-0) output signal < alc limiter detection level (lmth1-0)? during the alc recovery operation, the waiting timer of alc recovery operation is reset. when ?alc recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of alc recovery operation starts. the alc operation corresponds to the im pulse noise. when the impulse noise is input, the alc recovery operation becomes faster than a normal recovery operation (fast rec overy operation). when large noise is input to microphone instantaneously, the quality of small signal level in the large noise can be improved by this fast recovery operation. the speed of fast recovery operati on is set by rfst1-0 bits ( table 30 ). alc recovery oper ation waiting period wtm2 wtm1 wtm0 8khz 16khz 44.1khz 0 0 0 128/fs 16ms 8ms 2.9ms (default) 0 0 1 256/fs 32ms 16ms 5.8ms 0 1 0 512/fs 64ms 32ms 11.6ms 0 1 1 1024/fs 128ms 64ms 23.2ms 1 0 0 2048/fs 256ms 128ms 46.4ms 1 0 1 4096/fs 512ms 256ms 92.9ms 1 1 0 8192/fs 1024ms 512ms 185.8ms 1 1 1 16384/fs 2048ms 1024ms 371.5ms table 27. alc recovery operation waiting period rgain1 rgain0 gain step 0 0 1 step 0.375db (default) 0 1 2 step 0.750db 1 0 3 step 1.125db 1 1 4 step 1.500db table 28. alc recovery gain step
[ak4671] ms0666-e-02 2010/06 - 69 - ref7-0 bits gain (db) step f1h +36.0 f0h +35.625 efh +35.25 : : (default) e1h +30.0 : : 92h +0.375 91h 0.0 90h ? 0.375 : : 2h ? 53.625 1h ? 54.0 0.375db 0h mute table 29. reference level at alc recovery operation rfst1 bit rfst0 bit recovery speed 0 0 4 times (default) 0 1 8 times 1 0 16times 1 1 n/a table 30. fast recovery speed setting (n/a: not available)
[ak4671] ms0666-e-02 2010/06 - 70 - 3. example of alc operation table 31 and table 32 show the examples of the alc setting for mic recording and playback, respectively. fs=8khz fs=44.1khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelmn limiter zero crossing det ection 0 enable 0 enable ztm1-0 zero crossing timeout period * ztm1-0 bits should be equal to or shorter than wtm2-0 bits. 01 32ms 11 23.2ms wtm2-0 recovery waiting period 001 32ms 100 46.4ms ref7-0 maximum gain at recove ry operation e1h +30db e1h +30db ivl7-0, ivr7-0 gain of ivol e1h +30db e1h +30db lmat1-0 limiter att step 00 1 step 00 1 step rgain1-0 recovery gain step 00 1 step 00 1 step rfst1-0 fast recovery speed 00 4 times 00 4 times alc alc enable 1 enable 1 enable table 31. example of the alc setting (recording path) fs=8khz fs=44.1khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelmn limiter zero crossing det ection 0 enable 0 enable ztm1-0 zero crossing timeout period 01 32ms 11 23.2ms wtm2-0 recovery waiting period *wtm2-0 bits should be the same or longer data as ztm1-0 bits 001 32ms 100 46.4ms ref5-0 maximum gain at recove ry operation a1h +6db a1h +6db ivl7-0, ivr7-0 gain of ivol 91h 0db 91h 0db lmat1-0 limiter att step 00 1 step 00 1 step rgain1-0 recovery gain step 00 1 step 00 1 step rfst1-0 fast recovery speed 00 4 times 00 4 times alc alc enable 1 enable 1 enable table 32. example of the alc setting (playback path)
[ak4671] ms0666-e-02 2010/06 - 71 - the following registers should not be ch anged during the alc operation. these b its should be changed after the alc operation is finished by alc bit = ?0?. ? lmth1-0, lmat1-0, wtm2-0, ztm1-0, rgain1-0, ref7-0, zelmn, rfst1-0 manual mode * the value of ivol should be the same or smaller than ref?s wr (ivl7-0) wr (ivr7-0) wr (ref7-0) wr (lmth1-0, rgain1-0, lmat1-0, zelmn) example: limiter = zero crossing enable recovery cycle = 32ms@8khz zero crossing timeout period = 32ms@8khz limiter and recovery step = 1 fast recovery speed = 4 step gain of ivol = +30db maximum gain = +30.0db limiter detection level = ? 4.1dbfs alc bit = ?1? (1) addr=12h, data=e1h (2) addr=13h, data=e1h (5) addr=17h, data=01h (3) addr=14h, data=e1h wr (alc = ?1?) wr (ztm1-0, wtm2-0, rfst1-0) (4) addr=16h, data=05h (6) addr=18h, data=03h alc operation note : wr : write figure 62. registers set-up sequence at alc operation
[ak4671] ms0666-e-02 2010/06 - 72 - input digital volume (manual mode) the input digital volume becomes a manual mode when alc bit is ?0?. this mode is used in the case shown below. 1. after exiting reset state, set-up the registers fo r the alc operation (ztm1-0, lmth1-0 and etc) 2. when the registers for the alc operation (limiter period, recovery period and etc) are changed. for example, in case of changing the sampling frequency. 3. when ivol is used as a manual volume. ivl7-0 and ivr7-0 bits set the gain of the volume control ( table 33 ). when ivolc bit is ?0?, ivl7-0 and ivr7-0 bits control lch and rch volume values indepe ndently. when ivolc bit is ?1?, ivl7 -0 bits controls both channels. the ivol value is changed at zero crossing or timeout. zero cr ossing timeout period is set by ztm1-0 bits. if ivl7-0 or ivr7-0 bits are written during pmadl=pmadr bits = ?0?, ivol operation starts w ith the written values at the end of the adc initialization cycle after pmadl or pmadr bit is changed to ?1?. ivl7-0 bits ivr7-0 bits gain (db) step f1h +36.0 f0h +35.625 efh +35.25 : : 92h +0.375 (default) 91h 0.0 90h ? 0.375 : : 03h ? 53.25 02h ? 53.625 01h ? 54 0.375db 00h mute table 33. input digital volume setting side tone volume (svola) the ak4671 has the channel independent side tone volume (5 levels, 6db st ep). the volume can be set by the sval/r2-0 bits. the volume is included at mixing path fro m alc to 5-band eq. the output data of alc is changed from 0 to ?24db. svl2-0 gain 0h 0db (default) 1h ? 6db 2h ? 12db 3h ? 18db 4h ? 24db others n/a table 34. side tone volume a c ode table (n/a: not available)
[ak4671] ms0666-e-02 2010/06 - 73 - 5-band equalizer the ak4671 has 5-band equalizer before dac of stereo codec. the center frequencies and cut/boost amount are the followings. ? center frequency: 100hz, 250hz, 1khz, 3.5khz and 10khz ( note 62 , note 63 , note 64 ) ? cut/boost amount: ?10.5db +12db, 1.5db step note 62. these are the frequencies when the sampling freque ncy is 44.1khz. these frequencies are proportional to the sampling frequency. note 63. 100hz is not center frequency but the freque ncy component lower than 100hz is controlled. note 64. 10khz is not center frequency but the freque ncy component higher than 10khz is controlled. eq bit controls on/off of this equalizer and these boos t amount are set by eqa3-0, eqb3-0, eqc3-0, eqd3-0 and eqe3-0 bits, respectively, as shown in table 35 . eqa3-0: select the boost level of 100hz eqb3-0: select the boost level of 250hz eqc3-0: select the boost level of 1khz eqd3-0: select the boost level of 3.5khz eqe3-0: select the boost level of 10khz eqx3-0 boost amount 0h +12.0db 1h +10.5db 2h +9.0db 3h +7.5db : : 8h 0db (default) : : dh ? 7.5db eh ? 9.0db fh ? 10.5db table 35. boost amount of 5-band equalizer
[ak4671] ms0666-e-02 2010/06 - 74 - digital output volume the ak4671 has a digital output volume ( 256 levels, 0.5db step, mute). the volume can be set by the ovl7-0 and ovr7-0 bits. the volume is included in front of a dac block. the input data of dac is changed from +12 to ?115db or mute. when the ovolc bit = ?1?, the ovl7-0 bits contro l both lch and rch attenuation levels. when the ovolc bit = ?0?, the ovl7-0 bits control lch level and ovr7-0 bits cont rol rch level. this volume has a soft transition function. the ovtm bit sets the transition time between set values of ovl/r7-0 bits as either 1061/fs or 256/fs ( table 37 ). when ovtm bit = ?0?, a soft transition betw een the set values occurs (1062 levels ). it takes 1061/fs (=24ms@fs=44.1khz) from 00h (+12db) to ffh (mute). ovl/r7-0 gain step 00h +12.0db 01h +11.5db 02h +11.0db : : (default) 18h 0db : : fdh ? 114.5db feh ? 115.0db 0.5db ffh mute ( ? ) table 36. digital volume code table transition time between dvl/r7-0 bits = 00h and ffh ovtm bit setting fs=8khz fs=44.1khz 0 1061/fs 133ms 24ms (default) 1 256/fs 32ms 6ms table 37. transition time setti ng of digital output volume
[ak4671] ms0666-e-02 2010/06 - 75 - soft mute soft mute operation is performed in th e digital domain. when the smute bit is changed to ?1?, the output signal is attenuated to ? (?0?) during the cycle set by the ovtm bit. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the value set by the ovl/r 7-0 bits during the cycle set of the ovtm bit. if the soft mute is cancelled within the cycle set by the ovtm bit af ter starting the operation, the attenuation is discontinued and returned to the valu e set by the ovl/r7-0 bits. the soft mu te is effective for changing the signal source without stopping th e signal transmission ( figure 63 ). smute bit a ttenuation ovtm bit ovl/r7-0 bits - ovtm bit gd gd (1) (2) (3) a nalog output figure 63. soft mute function (1) the output signal is attenuated until ? (?0?) in the cycle set by the ovtm bit. (2) analog output corresponding to digita l input has the group delay (gd). (3) if the soft mute is cancelled within th e cycle set by the ovtm bit, the attenua tion is discounted and returned to the value set by the ovl/r7-0 bits.
[ak4671] ms0666-e-02 2010/06 - 76 - digital volume for recording of received voice (datt-b) the ak4671 has a digital output volume ( datt-b: 256 levels, 0.5db step, mute) for recording of received voice. the volume can be set by the bvl7-0 bits. the volume is included in front of an src-b block. the input data of src-b is changed from +12 to ?115db or mute. this volume has a soft tr ansit function. the transition time between set values of bvl7-0 bits is 256/fs2. it takes 256/fs2 (= 32ms@fs2=8khz) from 00h (+12db) to ffh (mute). bvl7-0 gain step 00h +12.0db 01h +11.5db 02h +11.0db : : (default) 18h 0db : : fdh ? 114.5db feh ? 115.0db 0.5db ffh mute ( ? ) table 38. digital volume b code table digital volume for received voice (datt-c) the ak4671 has a digital output volume ( datt-c: 256 levels, 0.5db step, mute) for received voice. the volume can be set by the cvl7-0 bits. the volume is included in front of sdtob output. the input data of src-c is changed from +12 to ?115db or mute. this volume has a soft transition function. the transition time between set values of cvl7-0 bits is 256/fs2. it takes 256/fs2 (=32ms@fs2=8khz) from 00h (+12db) to ffh (mute). cvl7-0 gain step 00h +12.0db 01h +11.5db 02h +11.0db : : (default) 18h 0db : : fdh ? 114.5db feh ? 115.0db 0.5db ffh mute ( ? ) table 39. digital volume c code table side tone volume for b/t phone call (svolb) the ak4671 has the side tone volume (5 le vels, 6db step) for b/t phone call. the volume can be set by the svl2-0 bits. the volume is included at mixing path from src-a to datt- c. the output data of src-a is changed from 0 to ?24db. svb2-0 gain 0h 0db (default) 1h ? 6db 2h ? 12db 3h ? 18db 4h ? 24db others n/a table 40. side tone volume b c ode table (n/a: not available)
[ak4671] ms0666-e-02 2010/06 - 77 - digital volume for b/t mic input (bivol) the ak4671 has the digital volume (5 levels, 6db step) for b/t mic input. the volume can be set by the biv2-0 bits. the volume is included at sdtib input. the input data is changed from 0 to ?24db. biv2-0 gain 0h 0db (default) 1h ? 6db 2h ? 12db 3h ? 18db 4h ? 24db others n/a table 41. sdtib volume code table (n/a: not available) path & mixing setting of digital block ( figure 57 ) pmadl and pmadr bits set both adc power management and output data selection. in case of mono operation, the same data is output to both channel slots. pmadl pmadr adc lch data adc rch data 0 0 all ?0? all ?0? (default) 0 1 rch input signal rch input signal 1 0 lch input signal lch input signal 1 1 lch input signal rch input signal table 42. adc mono/stereo select pfsel bit select the input data of programmable filter. pfsel programmable filter input 0 adc output (selected by table 42 ) (default) 1 sdti input (selected by table 48 ) table 43. programmable f ilter input signal select when adm bit is ?1?, alc output data is output to both channels of sdto and svola as (l+r)/2, respectively. adm lch rch 0 l r (default) 1 (l+r)/2 (l+r)/2 table 44. alc output mono mixing
[ak4671] ms0666-e-02 2010/06 - 78 - sdol1-0 and sdor1-0 bits set the data mixing for each channel of sdto from the data selected by table 44 and src-b output data. sdol1 sdol0 sdto lch 0 0 lch signal selected by table 44 (default) 0 1 src-b 1 0 (lch signal selected by table 44 ) + (src-b) 1 1 n/a table 45. sdto lch output mixing (n/a: not available) sdor1 sdor0 sdto rch 0 0 rch signal selected by table 44 (default) 0 1 src-b 1 0 (rch signal selected by table 44 ) + (src-b) 1 1 n/a table 46. sdto rch output mixing (n/a: not available) when sdod bit is ?1?, sdto output data can be disabled (fixed to ?l?). input data of svola is not disabled. sdod sdto 0 enable (output) (default) 1 disable (?l?) table 47. sdto disable sdim1-0 bits select stereo or mono of sdti input data. in case of mono mode, th e same data is input to both channels. sdim1 sdim0 lch rch 0 0 l r (default) 0 1 l l 1 0 r r 1 1 n/a table 48. sdti stereo/mono select (n/a: not available) pfmxl1-0 and pfmxr1-0 bits set the da ta mixing for each channel of 5-ba nd eq from the data selected by table 48 and svola output data. pfmxl1 pfmxl0 5-band eq lch input 0 0 lch signal selected by table 48 (default) 0 1 svola lch 1 0 (lch signal selected by table 48 ) + (svola lch) 1 1 n/a table 49. 5-band eq lch input mixing 1 (n/a: not available) pfmxr1 pfmxr0 5-band eq rch input 0 0 rch signal selected by table 48 (default) 0 1 svola rch 1 0 (rch signal selected by table 48 ) + (svola rch) 1 1 n/a table 50. 5-band eq rch input mixing 1 (n/a: not available)
[ak4671] ms0666-e-02 2010/06 - 79 - srmxl1-0 and srmxr1-0 bits set the data mixing for each channel of 5-band eq from the data selected by table 49 / table 50 and svola output data. srmxl1 srmxl0 5-band eq lch input 0 0 signal selected by table 49 (default) 0 1 src-b 1 0 (signal selected by table 49 ) + (src-b) 1 1 n/a table 51. 5-band eq lch input mixing 2 (n/a: not available) srmxr1 srmxr0 5-band eq rch input 0 0 signal selected by table 50 (default) 0 1 src-b 1 0 (signal selected by table 50 ) + (src-b) 1 1 n/a table 52. 5-band eq rch input mixing 2 (n/a: not available) dam and mixd bits set the data mixing for dac input. dam mixd lch rch 0 x l r (default) 1 0 l+r l+r 1 1 (l+r)/2 (l+r)/2 table 53. dac mono mixing (x: don?t care) sra1-0 and mixd bits set the data mixing for src-a input. sra1 sra0 mixd src-a 0 0 x l (default) 0 1 x r 1 0 0 l+r 1 0 1 (l+r)/2 1 1 x n/a table 54. src-a input mixing (x: d on?t care, n/a: not available) sdoa bit selects the output data of sdtoa. sdoa sdtoa 0 src-a (default) 1 sdtib table 55. sdtoa output select when sdoad bit is ?1?, sdtoa output data can be disabled (fixed to ?l?). i nput data of svolb is not disabled. sdoad sdtoa 0 enable (output) (default) 1 disable (?l?) table 56. sdtoa disable
[ak4671] ms0666-e-02 2010/06 - 80 - sbmx1-0 bits set the data mixing from sdtia input and svolb output. the mixed data is output to sdtob via datt-c. sbmx1 sbmx0 datt-c input 0 0 sdtia (default) 0 1 svolb 1 0 (sdtia) + (svolb) 1 1 n/a table 57. sdtob mixing (n/a: not available) when sdobd bit is ?1?, sdtob output da ta can be disabled (fixed to ?l?). sdobd sdtob 0 enable (output) (default) 1 disable (?l?) table 58. sdtob disable bvmx1-0 bits set the data mixing for src-b from sdtia input (datt-b output) and sd tib input (bivol output). bvmx1 bvmx0 src-b input 0 0 sdtia (default) 0 1 sdtib 1 0 (sdtia) + (sdtib) 1 1 n/a table 59. src-b input mixing (n/a: not available)
[ak4671] ms0666-e-02 2010/06 - 81 - analog mixing: single-ended input (lin1/ri n1/lin2/rin2/lin3/rin3/lin4/rin4 pins) ak4671 supports analog mixing function from each line input to each line output ( figure 64 ). when the analog mixing is used, a/d converter is also available if pm adl or pmadr bit is ?1?. when pmainl1=pmainr1=pmainl2=pmainr2=pmainl 3=pmainr3=pmainl4=pmainr4=pmmicl=pmmicr bits = ?1?, the input resistance of lin1/rin1/ lin2/rin2/lin3/rin3/lin4/rin4 pins becomes 25k (typ) at mgnl/r0 bits = ?0? and 20k (typ) at mgnl/r0 bits = ?1?, respectively. l1g1-0, l2g1-0, l3g1-0, l4g1-0 and lpg1-0 bits adjust the gain for each path ( table 60 , table 61 , table 62 , table 63 , table 64 ). lin1/in1+ pin a dc lch rin1/in1 ? pin inl4-0 bits mdif1 bit mdif3 bit lin2/in2+ pin a dc rch rin2/in2 ? pin inr4-0 bits mdif2 bit mdif4 bit ak4671 lin3/in3+ pin rin3/in3 ? pin mic-amp lch mic-amp rch pmainl3 bit pmainr3 bit pmainl2 bit pmainr2 bit pmainl1 bit pmainr1 bit lin4/in4+ pin rin4/in4 ? pin pmloopl bit pmloopr bit pmainl4 bit pmainr4 bit figure 56, 57, 59, 60 figure 62, 63 figure 66, 67, 69, 70 lout1 pin rout1 pin lout2 pin rout2 pin lout3 pin rout3 pin figure 64. analog mixing circuit
[ak4671] ms0666-e-02 2010/06 - 82 - l1g1 bit l1g0 bit gain 0 0 0db (default) 0 1 +6db 1 0 ? 6db 1 1 n/a table 60. lin1/rin1 (or in1+/ ? ) mixing gain (typ) (n/a: not available) l2g1 bit l2g0 bit gain 0 0 0db (default) 0 1 +6db 1 0 ? 6db 1 1 n/a table 61. lin2/rin2 (or in2+/ ? ) mixing gain (typ) (n/a: not available) l3g1 bit l3g0 bit gain 0 0 0db (default) 0 1 +6db 1 0 ? 6db 1 1 n/a table 62. lin3/rin3 (or in3+/ ? ) mixing gain (typ) (n/a: not available) l4g1 bit l4g0 bit gain 0 0 0db (default) 0 1 +6db 1 0 ? 6db 1 1 n/a table 63. lin4/rin4 (or in4+/ ? ) mixing gain (typ) (n/a: not available) lpg1 bit lpg0 bit gain 0 0 0db (default) 0 1 +6db 1 0 ? 6db 1 1 n/a table 64. mic-amp mixing gain (typ) (n/a: not available) analog mixing: full-diffe rential input (in1+/in1 ? /in2+/in2 ? /in3+/in3 ? /in4+/in4 ? pins) when mdif1, mdif2, mdif3 and mdif4 bits are ?1?, lin1/rin1, lin2/rin2, lin3/rin3 and lin4/rin4 pins become in1+/ ? , in2+/ ? , in3+/ ? and in4+/ ? pins, respectively, and analog mixing is availble. when the analog mixing is used, a/d converter is also available if pm adl or pmadr bit is ?1?. when pmainl1=pmainr1=pmainl2=pmainr2=pmainl 3=pmainr3=pmainl4=pmainr4=pmmicl=pmmicr bits = ?1?, the input resistance of in1+/ ? , in2+/ ? , in3+/ ? and in4+/ ? pins becomes 25k (typ) at mgnl/r0 bits = ?0? and 20k (typ) at mgnl/r0 bits = ?1?, respectively. l1g1-0, l2g1-0, l3g1-0, l4g1-0 and lpg1-0 bits adjust the gain for each path ( table 60 , table 61 , table 62 , table 63 , table 64 ).
[ak4671] ms0666-e-02 2010/06 - 83 - stereo line output (lout1/rout1 pins) when dacl and dacr bits are ?1?, lch/rch signal of dac is output from the lout 1/rout1 pins which is single-ended. when dacl and dacr bits are ?0?, output signal is muted and lout 1/rout1 pins output vcom voltage. the load impedance is 10k (min.). when the pmlo1=pmro1=lops1 bits = ?0?, lout1/rout1 enters power-down mode and the output is pulled-down to vss1 by 100k (typ). when the lops1 b it is ?1?, lout1/rout1 enters power-save mode. pop noise at power-up/down can be reduced by cha nging pmlo1 and pmro1 bits at lops1 bit = ?1?. in this case, output signal line should be pulled-down to vss1 by 20k after ac coupled as figure 65 . rise/fall time is 300ms(max) at c=1 f and avdd=3.3v. when pmlo1=pmro1 bits = ?1? and lops1 bit = ?0?, lout1/rout1 is in normal operation. l1vl3-0 bits control the volume of lout1/rout1. when lom bit = ?1?, dac output signal is output to lout1 and rout1 pins as (l+r) mono signal. when loopm bit = ?1?, the mic-amp signal is output to lout1 and rout1 pins as (l+r) mono signal. lops1 pmlo1 mode lout1 pin 0 power-down pull-down to vss1 (default) 0 1 normal operation normal operation 0 power-save fall down to vss1 1 1 power-save rise up to vcom table 65. stereo line out put mode select (lout1) lops1 pmro1 mode rout1 pin 0 power-down pull-down to vss1 (default) 0 1 normal operation normal operation 0 power-save fall down to vss1 1 1 power-save rise up to vcom table 66. stereo line out put mode select (rout1) l1vl2-0 attenuation 6h +6db 5h 0db (default) 4h ? 6db 3h ? 12db 2h ? 18db 1h ? 24db 0h mute table 67. stereo line output volume setting lout1 rout1 1 f 220 20k figure 65. external circuit for stereo line out put (in case of using pop noise reduction circuit)
[ak4671] ms0666-e-02 2010/06 - 84 - pmlo1 bit pmro1 bit lops1 bit lout1 pin rout1 pin (1) (2) normal output (3) (4) (5) (6) 300 ms 300 ms figure 66. stereo line output control sequence (in case of usi ng pop noise reduction circuit) (1) set lops1 bit = ?1?. stereo line output enters the power-save mode. (2) set pmlo1=pmro1 bits = ?1?. stereo line output exits the power-down mode. lout1 and rout1 pins rise up to vcom volta ge. rise time is 200ms (max 300ms) at c=1 f and avdd=3.3v. (3) set lops1 bit = ?0? after lout1 and rout1 pins rise up. stereo line output exits the power-save mode. stereo line output is enabled. (4) set lops1 bit = ?1?. stereo lin e output enters power-save mode. (5) set pmlo1=pmro1 bits = ?0?. stereo line output enters power-down mode. lout1 and rout1 pins fall down to vss1. fall time is 200ms (max 300ms) at c=1 f and avdd=3.3v. (6) set lops1 bit = ?0? after lout1 and rout1 pins fall down. stereo line output exits the power-save mode.
[ak4671] ms0666-e-02 2010/06 - 85 - dacl, dacr, lom, linl1, rinr1, linl2, rinr2, linl 3, rinr3, linl4, rinr4, loopl, loopr and loopm bits control each path switch. m i x 0db dacl bit lout1 pin mic-amp lch stereo dac lch linl2 bit +6/0/ ? 6db linl1 bit loopl bit +6/0/ ? 6db +6/0/ ? 6db datt l1vl2-0 bits linl4 bit linl3 bit m i x dacl bit x lom bit rout1 pin rinr2 bit rinr1 bit loopl bit x loopm bit l1vl2-0 bits rinr4 bit rinr3 bit 0db dacr bit mic-amp rch stereo dac rch +6/0/ ? 6db loopr bit +6/0/ ? 6db +6/0/ ? 6db datt loopr bit x loopm bit dacr bit x lom bit lin4 pin lin2 pin +6/0/ ? 6db +6/0/ ? 6db lin3 pin lin1 pin rin3 pin rin4 pin rin2 pin rin1 pin +6/0/ ? 6db +6/0/ ? 6db figure 67. lout1/rout1 mixing circuit (m dif1=mdif2=mdif3=mdi f4 bits = ?0?)
[ak4671] ms0666-e-02 2010/06 - 86 - m i x 0db dacl bit lout1 pin mic-amp lch stereo dac lch in3+/ ? pins linl2 bit in1+/ ? pins +6/0/ ? 6db linl1 bit loopl bit +6/0/ ? 6db +6/0/ ? 6db datt l1vl2-0 bits linl4 bit linl3 bit m i x dacl bit x lom bit rout1 pin rinr2 bit rinr1 bit loopl bit x loopm bit l1vl2-0 bits rinr4 bit rinr3 bit 0db dacr bit mic-amp rch stereo dac rch in4+/ ? pins in2+/ ? pins +6/0/ ? 6db loopr bit +6/0/ ? 6db +6/0/ ? 6db datt loopr bit x loopm bit dacr bit x lom bit figure 68. lout1/rout1 mixing circuit (m dif1=mdif2=mdif3=mdi f4 bits = ?1?)
[ak4671] ms0666-e-02 2010/06 - 87 - receiver-amp (rcp/rcn pins) when rcv bit = ?1?, lout1/rout1 pins become rcp/ rcn pins, respectively. lch/rch signal of dac or lin1/rin1/lin2/rin2/lin3/rin3/lin4/rin4 is output from the rcp/rcn pins which is btl as (l+r) signal. the load impedance is 32 (min). when the pmlo1 = pmro1 bits = ?0 ?, the mono receiver output enters power-down mode and the output is hi-z. when the pmlo1 = pmro1 bits = ?1? and lops1 bit = ?1?, mono receiver output enters power-save mode. pop noise at power- up/down can be reduced by changing pmlo1 and pmro1 bits at lops1 bit = ?0?. when pmlo1 = pmro1 bits = ?1? and lops1 bit = ?0?, mono receiver output enters in normal operation. l1vl3-0 bits control the vol ume of mono receiver output. l1vl2-0 attenuation 6h +12db 5h +6db (default) 4h 0db 3h ? 6db 2h ? 12db 1h ? 18db 0h mute table 68. mono receiver output volume setting pmlo1/ro1 lops1 mode rcp rcn 0 x power-down hi-z hi-z (default) 1 power-save hi-z vcom 1 0 normal operation normal operation normal operation table 69. receiver-amp mode setting (x: don?t care) pmlo1 bit pmro1 bit lops1 bit rcp pin rcn pin vcom vcom hi-z hi-z hi-z hi-z >1ms >0 figure 69. power-up/power- down timing for receiver-amp
[ak4671] ms0666-e-02 2010/06 - 88 - dacl, dacr, linl1, rinr1, linl2, ri nr2, linl3, rinr3, linl4, rinr4, loopl and loopr bits control each path switch. when mdif1/2/3/4 bits = ?1?, ri nr1/2/3/4 bits should be ?0?. lin3 pin m i x linl3 bit lin4 pin linl4 bit 0db dacr bit rcp/rcn pins mic-amp lch stereo dac rch lin2 pin linl2 bit lin1 pin linl1 bit loopl bit rin3 pin rinr3 bit rin4 pin rinr4 bit 0db dacl bit mic-amp rch stereo dac lch rin2 pin rinr2 bit rin1 pin rinr1 bit loopr bit +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db datt datt l1vl2-0 bits figure 70. receiver mixing circuit (mdif1=mdif2=mdi f3=mdif4 bits = ?0?)
[ak4671] ms0666-e-02 2010/06 - 89 - m i x linl3 bit linl4 bit 0db dacr bit rcp/rcn pins mic-amp lch stereo dac rch linl2 bit linl1 bit loopl bit 0db dacl bit mic-amp rch stereo dac lch loopr bit +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db datt datt l1vl2-0 bits in3+/ ? pins in1+/ ? pins in4+/ ? pins in2+/ ? pins figure 71. receiver mixing circuit (mdif1=mdif2=mdi f3=mdif4 bits = ?1?)
[ak4671] ms0666-e-02 2010/06 - 90 - headphone output (lout2/rout2 pins) power supply voltage for the lout2/rout2 is supplie d from the avdd pin and centered on the 0.5 x avdd (typ) voltage. the load resistance is 16 (min). hpg3-0 bits control the output volume ( table 70 ). when lom2 bit = ?1?, dac output signal is output to lout2 and rout2 pins as (l+r) mono signal. when loopm2 bit = ?1?, the mic-amp signal is output to lout2 and rout2 pins as (l+r) mono signal. hpg3-0 attenuation dh +6db ch +3db bh 0db (default) ah ? 3db : : : : 2h ? 27db 1h ? 30db 0h mute table 70. lout2/rout2 output volume when the muten bit is ?0?, the co mmon voltage of lout2/rout2 falls a nd the outputs (lout2 and rout2 pins) change to ?l? (vss1). when the muten bit is ?1?, the common voltage rise s to vcom voltage. a capacitor between the mutet pin and ground reduces pop noise at power-up. rise/fall time constant is in proportional to avdd voltage and the capacitor at mutet pin. [example]: a capacitor between the mutet pin and ground = 1.0 f, avdd=3.3v: rise/fall time constant: = 100ms(typ), 250ms(max) time until the common goes to vss1 when muten bit = ?1? ? ?0?: 500ms(max) when pmlo2, pmro2, pmlo2s and pmro2s bits are ?0 ?, the lout2/rout2 is powered-down, and the outputs (lout2 and rout2 pins) go to ?l? (vss1). pmlo2 bit, pmro2 bit, pmlo2s bit, pmro2s bit (1) (2) (4) (3) muten bit lout2 pin, rout2 pin figure 72. power-up/power-dow n timing for lout2/rout2 (1) lout2/rout2 power-up (pmlo2, pm ro2, pmlo2s, pmro2s bit = ?1 ?). the outputs are still vss1. (2) lout2/rout2 common voltage rises up (muten bit = ?1?). (3) lout2/rout2 common voltage falls down (muten bit = ?0?). (4) lout2/rout2 power-down (pmlo2, pmro2, pmlo2s, pmro2s bit = ?0?). the outputs are vss1. if the power supply is switched off or lout2/rout 2 is powered-down before the common voltage goes to vss1, some pop noise occurs.
[ak4671] ms0666-e-02 2010/06 - 91 - dachl, dachr, lom2, linh1, rinh1, linh2, rinh2, li nh3, rinh3, linh4, rinh4, loophl, loophr and loopm2 bits control each path switch. m i x 0db dachl bit lout2 pin mic-amp lch stereo dac lch linh2 bit +6/0/ ? 6db linh1 bit loophl bit +6/0/ ? 6db +6/0/ ? 6db datt hpg3-0 bits linh4 bit linh3 bit m i x dachl bit x lom2 bit rout2 pin rinh2 bit rinh1 bit loophl bit x loopm2 bit hpg3-0 bits rinh4 bit rinh3 bit 0db dachr bit mic-amp rch stereo dac rch +6/0/ ? 6db loophr bit +6/0/ ? 6db +6/0/ ? 6db datt loophr bit x loopm2 bit dachr bit x lom2 bit lin4 pin lin2 pin +6/0/ ? 6db +6/0/ ? 6db lin3 pin lin1 pin rin3 pin rin4 pin rin2 pin rin1 pin +6/0/ ? 6db +6/0/ ? 6db figure 73. lout2/rout2 mixing circuit (m dif1=mdif2=mdif3=mdi f4 bits = ?0?)
[ak4671] ms0666-e-02 2010/06 - 92 - m i x 0db dachl bit lout2 pin mic-amp lch stereo dac lch in3+/ ? pins linh2 bit in1+/ ? pins +6/0/ ? 6db linh1 bit loophl bit +6/0/ ? 6db +6/0/ ? 6db datt hpg3-0 bits linh4 bit linh3 bit m i x dachl bit x lom2 bit rout2 pin rinh2 bit rinh1 bit loophl bit x loopm2 bit hpg3-0 bits rinh4 bit rinh3 bit 0db dachr bit mic-amp rch stereo dac rch in4+/ ? pins in2+/ ? pins +6/0/ ? 6db loophr bit +6/0/ ? 6db +6/0/ ? 6db datt loophr bit x loopm2 bit dachr bit x lom2 bit figure 74. lout2/rout2 mixing circuit (m dif1=mdif2=mdif3=mdi f4 bits = ?1?)
[ak4671] ms0666-e-02 2010/06 - 93 - stereo line output 3 (lout3/rout3 pins) when dacsl and dacsr bits are ?1?, lch/rch signal of dac is output from the l out3/rout3 pins which is single-ended. when dacsl and dacsr bits are ?0?, out put signal is muted and lout 3/rout3 pins output vcom voltage. the load impedance is 10k (min.). when the pmlo3=pmro3=lops3 bits = ?0?, lout3/rout3 enters power-down mode and the output is pulled-down to vss1 by 100k (typ). when the lops3 b it is ?1?, lout3/rout3 enters power-save mode. pop noise at power-up/down can be reduced by cha nging pmlo3 and pmro3 bits at lops3 bit = ?1?. in this case, output signal line should be pulled-down to vss1 by 20k after ac coupled as figure 75 . rise/fall time is 300ms(max) at c=1 f and avdd=3.3v. when pmlo3=pmro3 bits = ?1? and lops3 bit = ?0?, lout3/rout3 is in normal operation. l3vl3-0 bits control the volume of lout3/rout3. when lom3 bit = ?1?, dac output signal is output to lout3 and rout3 pins as (l+r) mono signal. when loopm3 bit = ?1?, the mic-amp signal is output to lout3 and rout3 pins as (l+r) mono signal. lops3 pmlo3 mode lout3 pin 0 power-down pull-down to vss1 (default) 0 1 normal operation normal operation 0 power-save fall down to vss1 1 1 power-save rise up to vcom table 71. stereo line out put mode select (lout3) lops3 pmro3 mode rout3 pin 0 power-down pull-down to vss1 (default) 0 1 normal operation normal operation 0 power-save fall down to vss1 1 1 power-save rise up to vcom table 72. stereo line out put mode select (rout3) l3vl1 l3vl0 attenuation 1 1 +3db 1 0 0db (default) 0 1 ? 3db 0 0 ? 6db table 73. stereo line output volume setting lout3 rout3 1 f 220 20k figure 75. external circuit for stereo line out put (in case of using pop noise reduction circuit)
[ak4671] ms0666-e-02 2010/06 - 94 - pmlo3 bit pmro3 bit lops3 bit lout3, rout3 pins (1) (2) normal output (3) (4) (5) (6) 300 ms 300 ms figure 76. stereo line output 3 control sequence (in case of us ing pop noise reduction circuit) (1) set lops3 bit = ?1?. stereo line output enters the power-save mode. (2) set pmlo3=pmro3 bits = ?1?. stereo line output exits the power-down mode. lout3 and rout3 pins rise up to vcom volta ge. rise time is 200ms (max 300ms) at c=1 f and avdd=3.3v. (3) set lops3 bit = ?0? after lout3 and rout3 pins rise up. stereo line output exits the power-save mode. stereo line output is enabled. (4) set lops3 bit = ?1?. stereo lin e output enters power-save mode. (5) set pmlo3=pmro3 bits = ?0?. stereo line output enters power-down mode. lout3 and rout3 pins fall down to vss1. fall time is 200ms (max 300ms) at c=1 f and avdd=3.3v. (6) set lops3 bit = ?0? after lout3 and rout3 pins fall down. stereo line output exits the power-save mode.
[ak4671] ms0666-e-02 2010/06 - 95 - dacsl, dacsr, lom3, lins1, rins1, lins2, rins2, li ns3, rins3, lins4, rins4, loopsl, loopsr and lom3 bits control each path switch. m i x 0db dacsl bit lout3 pin mic-amp lch stereo dac lch lins2 bit +6/0/ ? 6db lins1 bit loopsl bit +6/0/ ? 6db +6/0/ ? 6db datt l3vl1-0 bits lins4 bit lins3 bit m i x dacsl bit x lom3 bit rout3 pin rins2 bit rins1 bit loopsl bit x loopm3 bit l3vl1-0 bits rins4 bit rins3 bit 0db dacsr bit mic-amp rch stereo dac rch +6/0/ ? 6db loopsr bit +6/0/ ? 6db +6/0/ ? 6db datt loopsr bit x loopm3 bit dacsr bit x lom3 bit lin4 pin lin2 pin +6/0/ ? 6db +6/0/ ? 6db lin3 pin lin1 pin rin3 pin rin4 pin rin2 pin rin1 pin +6/0/ ? 6db +6/0/ ? 6db figure 77. lout3/rout3 mixing circuit (m dif1=mdif2=mdif3=mdi f4 bits = ?0?)
[ak4671] ms0666-e-02 2010/06 - 96 - m i x 0db dacsl bit lout3 pin mic-amp lch stereo dac lch in3+/ ? pins lins2 bit in1+/ ? pins +6/0/ ? 6db lins1 bit loopsl bit +6/0/ ? 6db +6/0/ ? 6db datt l3vl1-0 bits lins4 bit lins3 bit m i x dacsl bit x lom3 bit rout3 pin rins2 bit rins1 bit loopsl bit x loopm3 bit l3vl1-0 bits rins4 bit rins3 bit 0db dacsr bit mic-amp rch stereo dac rch in4+/ ? pins in2+/ ? pins +6/0/ ? 6db loopsr bit +6/0/ ? 6db +6/0/ ? 6db datt loopsr bit x loopm3 bit dacsr bit x lom3 bit figure 78. lout3/rout3 mixing circuit (m dif1=mdif2=mdif3=mdi f4 bits = ?1?)
[ak4671] ms0666-e-02 2010/06 - 97 - full-differential mono line output (lop/lon pins) when lodif bit = ?1?, lout3/rout3 pins become lo p/lon pins, respectively. lch/rch signal of dac or lin1/rin1/lin2/rin2/lin3/rin3/lin4/rin4 is output from the lop/lon pins which is full-differential as (l+r) signal. the load impedance is 10k (min) for lop and lon pins, respectively. when the pmlo3 = pmro3 bits = ?0?, the mono line output enters power-down m ode and the output is pulled-down to vss1. when the pmlo3 = pmro3 bits = ?1? and lops3 bit = ?1?, mono line output enters power-s ave mode. pop noise at powe r-up/down can be reduced by changing pmlo3 and pmro3 bits at lops3 bit = ?0?. when pmlo3 = pmro3 bits = ?1? and lops3 bit = ?0?, mono line output enters in normal operation. l3vl 1-0 bits set the volume of mono line output. l3vl1-0 attenuation 3h +9db 2h +6db (default) 1h +3db 0h 0db table 74. mono line output gain setting lops3 pmlo3/ro3 mode lout3 pin 0 power-down pull-down to vss1 (default) 0 1 normal operation normal operation 0 power-save fall down to vss1 1 1 power-save rise up to vcom table 75. mono line output mode setting pmlo 3 bit pmro3 bit lops3 bit lop, lon pins (1) (2) normal output (3) (4) (5) (6) 300 m s 300 m s figure 79. mono line output 3 c ontrol sequence (in case of usi ng pop noise reduction circuit) (1) set lops3 bit = ?1?. mono line output enters the power-save mode. (2) set pmlo3 = pmro3 bits = ?1?. mono line output exits the power-down mode. lop and lon pins rise up to vcom voltage . rise time is 200ms (max 300ms) at c=1 f and avdd=3.3v. (3) set lops3 bit = ?0? after lop and lon pins rise up. mono line output exits the power-save mode. mono line output is enabled. (4) set lops3 bit = ?1?. mono line output enters power-save mode. (5) set pmlo3 = pmro3 bits = ?0?. mono line output enters power-down mode. lop and lon pins fall down to vss1. fall time is 200ms (max 300ms) at c=1 f and avdd=3.3v. (6) set lops3 bit = ?0? after lop and lon pins fall down. mono line output exits the power-save mode.
[ak4671] ms0666-e-02 2010/06 - 98 - dacsl, dacsr, lins1, rins1, lins2, rins2, lins3, rins 3, lins4, rins4, loopsl and loopsr bits control each path switch. when mdif1/2/3/4 bits = ?1?, ri ns1/2/3/4 bits should be ?0?. lin3 pin m i x lins3 bit lin4 pin lins4 bit 0db dacsr bit lop/lon pins mic-amp lch stereo dac rch lin2 pin lins2 bit lin1 pin lins1 bit loopsl bit rin3 pin rins3 bit rin4 pin rins4 bit 0db dacsl bit mic-amp rch stereo dac lch rin2 pin rins2 bit rin1 pin rins1 bit loopsr bit +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db datt datt l3vl1-0 bits figure 80. mono line output mixing circuit (mdif1=mdif2=mdif3=m dif4 bits = ?0?)
[ak4671] ms0666-e-02 2010/06 - 99 - m i x lins3 bit lins4 bit 0db dacsr bit lop/lon pins mic-amp lch stereo dac rch lins2 bit lins1 bit loopsl bit 0db dacsl bit mic-amp rch stereo dac lch loopsr bit +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db +6/0/ ? 6db datt datt l3vl1-0 bits in3+/ ? pins in1+/ ? pins in4+/ ? pins in2+/ ? pins figure 81. mono line output mixing circuit (mdif1=mdif2=mdif3=m dif4 bits = ?1?)
[ak4671] ms0666-e-02 2010/06 - 100 - system clock (pcm i/f) a reference clock of pllbt is select ed among the input clocks to synca, bicka, syncb or bickb pin. the required clock to pcm i/f is ge nerated by an internal pllbt circuit. pllb t circuit is powered up by pmpcm bit. input frequency is selected by pllbt3-0 bits ( table 76 ). bcko2 bit select the output cl ock frequency of bicka or bickb pin ( table 77 ). ak4671 does not support master mode for both pcm i/ f a and b nor slave mode for both pcm i/f a and b. whether pcm i/f a or b should be set as slave mode . when pmpcm bit is ?0?, synca, bicka, syncb and bickb pins are hi-z. table 78 indicates the output data of sdtoa and sdtob pins in case of pmpcm bit = ?0? and during lock time in table 76, respectively. table 79 indicates the output clock at ma ster mode during lock time in table 76. r, c at vcocbt pin mode pllbt3 pllbt2 pllbt1 pllbt0 reference clock input pin frequency r c lock time (max) 0 0 0 0 0 synca 1fs2 6.8k 220n 260ms (default) 1 0 0 0 1 bicka 16fs2 10k 4.7n 40ms 2 0 0 1 0 bicka 32fs2 10k 4.7n 40ms 3 0 0 1 1 bicka 64fs2 10k 4.7n 40ms 4 0 1 0 0 syncb 1fs2 6.8k 220n 260ms 5 0 1 0 1 bickb 16fs2 10k 4.7n 40ms 6 0 1 1 0 bickb 32fs2 10k 4.7n 40ms 7 0 1 1 1 bickb 64fs2 10k 4.7n 40ms 11 1 0 1 1 bicka 48fs2 10k 4.7n 40ms 15 1 1 1 1 bickb 48fs2 10k 4.7n 40ms others n/a table 76. pllbt reference clock (n/a: not available) note 65. mode 1 is available at only fmta1 bit = ?0?. note 66. mode 5 is available at only fmtb1 bit = ?0?. bcko2 bit bicka/bickb output frequency 0 16fs2 (default) 1 32fs2 table 77. bicka/b output frequency mode pmpcm bit = ?0? after pmpcm bit = ?0? ?1? & before synca/syncb input pmpcm bit = ?1? during locktime 16bit linear l l 0000h 8bit a-law l h 11010101b 8bit -law l h 11111111b table 78. sdtoa, sdtob pins output data format synca, syncb bicka, bickb except for i 2 s l l i 2 s h l table 79. output clock during lock time
[ak4671] ms0666-e-02 2010/06 - 101 - a) pllbt reference clock: synca or bicka pin the pllbt circuit generates the required clock for pcm i/ f from synca or bicka. gene rated clocks are output via syncb and bickb pins. ak4671 phone module bicka sdtoa sdtia syncb sdti sdto sync synca 1fs2 16fs2 bick bickb sdtob sdtib sdti sdto 1fs2 16fs2 or 32fs2 bick sync bluetooth module figure 82. pcm i/f (pllbt reference clock: synca or bicka pin) b) pllbt reference clock: syncb or bickb pin the pllbt circuit generates the required clock for pcm i/ f from syncb or bickb. gene rated clocks are output via synca and bicka pins. ak4671 phone module bicka sdtoa sdtia syncb sdti sdto sync synca 1fs2 16fs2 or 32fs2 bick bickb sdtob sdtib sdti sdto 1fs2 16fs2 bick sync bluetooth module figure 83. pcm i/f (pllbt reference clock: syncb or bickb pin) pllbt should always be powered-up (pmpcm bit = ?1?) when ever src-a or src-b is in operation (pmsra bit = ?1? or pmsrb bit = ?1?). if pllbt is powered-down, the ak4671 ma y draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic interna lly. if pllbt is powered-down, src-a, src-b and src-c should be in the power-down mode (pmsra=pmsrb bits = ?0?).
[ak4671] ms0666-e-02 2010/06 - 102 - pcm i/f master mode/slave mode the pllbt2 bit selects either master or slave mode ( table 80 ). when either pcm i/f a or pcm i/f b is set in slave mode, the other is set in master mode. (for example, when pcm i/f b is set in slave mode, pcm i/f a is set in master mode.) when the ak4671 is power-down mode (pdn pin = ?l?) or pmpcm bit = ?0?, each clock pins (synca, bicka, syncb, bickb) of pcm i/f become a hi-z ( table 81 ). pllbt3-0 bits should be set when pmpcm bit = ?0? to avoid shorting out of the slave mode clock pins and master mode clock output. after setting the pdn pin = ?h?, the pcm i/f clock pins ar e the hi-z state until pmpcm b it becomes ?1?. the pcm i/f clock pins of master mode should be pulled-down or pulled- up by the resistor (about 100k ) externally to avoid the floating state. pllbt2 bit pcm i/f a synca, bicka pins pcm i/f b syncb, bickb pins 0 slave mode input master mode output (default) 1 master mode output slave mode input table 80. select pcm i/f master/slave mode pdn pin pmpcm bit synca, bicka pin syncb, bickb pin l - hi-z hi-z 0 hi-z hi-z h 1 i/o select by pllbt2 bit ( table 80 ) i/o select by pllbt2 bit ( table 80 ) table 81. pcm i/f clock i/o state
[ak4671] ms0666-e-02 2010/06 - 103 - pcm i/f a & b format ak4671 supports dual pcm i/f (pcm i/f a & pcm i/f b) that supports 3 kind of i/f (16bit linear, 8bit a-law and 8bit -law) independently ( table 82 and table 83 ). mode lawa1 lawa0 format 0 0 0 16bit linear (default) 1 0 1 n/a 2 1 0 8bit a-law 3 1 1 8bit -law table 82. pcm i/f a mode (n/a: not available) mode lawb1 lawb0 format 0 0 0 16bit linear (default) 1 0 1 n/a 2 1 0 8bit a-law 3 1 1 8bit -law table 83. pcm i/f b mode (n/a: not available) four types of data formats are available and are selected by setting the fmta1-0 and fmtb1-0 bits independently ( table 84 and table 85 ). in 16bit linear mode, the serial data is msb first, 2?s complement format. in 8bit a-law and -law mode, the serial data is msb first. pcm i/f formats can be used in both master a nd slave modes. synca/b and bicka/b are output from the ak4671 in master mode, but must be input to the ak4671 in slave mode. mode fmta1 fmta0 format bicka figure 0 0 0 short frame sync 16fs2 see table 86 (default) 1 0 1 long frame sync 16fs2 see table 88 2 1 0 msb justified 32fs2 figure 92 3 1 1 i 2 s 32fs2 figure 93 table 84. pcm i/f a format mode fmtb1 fmtb0 format bickb figure 0 0 0 short frame sync 16fs2 see table 87 (default) 1 0 1 long frame sync 16fs2 see table 89 2 1 0 msb justified 32fs2 figure 92 3 1 1 i 2 s 32fs2 figure 93 table 85. pcm i/f b format in modes 2 and 3, the sdtoa/b is clocked out on the falling edge (? ?) of bicka/b and the sdtia/b is latched on the rising edge (? ?). in modes 0 and 1, pcm i/f a timing is changed by bckpa and msbsa bits, and pcm i/f b timing is changed by bckpb and msbsb bits. when bckpa bit = ?0?, the sdtoa is clocked out on the rising edge (? ?) of bicka and the sdtia is latched on the falling edge (? ?). when bckpa bit = ?1?, the sdtoa is clocked out on the falling edge (? ?) of bicka and the sdtia is latched on the rising edge (? ?). msbsa bit can shift the msb position of sdtoa and sdtia by half period of bicka. when bckpb bit = ?0?, the sdtob is clocked out on the rising edge (? ?) of bickb and the sdtib is latched on the falling edge (? ?). when bckpb bit = ?1?, the sdtob is clocked out on the falling edge (? ?) of bickb and the sdtib is latched on the rising edge (? ?). msbsb bit can shift the msb position of sdtob and sdtib by half period of bickb.
[ak4671] ms0666-e-02 2010/06 - 104 - msbsa bckpa data interface format figure 0 0 msb of sdtoa is output by next rising edge (? ?) of the falling edge (? ?) of bicka after the rising edge (? ?) of synca. msb of sdtia is latched by the falling edge (? ?) of the bicka just after the output timing of sdtoa?s msb. figure 84 0 1 msb of sdtoa is output by next falling edge (? ?) of the rising edge (? ?) of bicka after the rising edge (? ?) of synca. msb of sdtia is latched by the rising edge (? ?) of the bicka just after the output timing of sdtoa?s msb. figure 85 1 0 msb of sdtoa is output by the 2nd rising edge (? ?) of bicka after the rising edge (? ?) of synca. msb of sdtia is latched by the falling edge (? ?) of the bicka just after the output timing of sdtoa?s msb. figure 86 1 1 msb of sdtoa is output by the 2nd falling edge (? ?) of bicka after the rising edge (? ?) of synca. msb of sdtia is latched by the rising edge (? ?) of the bicka just after the output timing of sdtoa?s msb. figure 87 table 86. pcm i/f a format in mode 0 msbsb bckpb data interface format figure 0 0 msb of sdtob is output by next rising edge (? ?) of the falling edge (? ?) of bickb after the rising edge (? ?) of syncb. msb of sdtib is latched by the falling edge (? ?) of the bickb just after the output timing of sdtob?s msb. figure 84 0 1 msb of sdtob is output by next falling edge (? ?) of the rising edge (? ?) of bickb after the rising edge (? ?) of syncb. msb of sdtib is latched by the rising edge (? ?) of the bickb just after the output timing of sdtob?s msb. figure 85 1 0 msb of sdtob is output by the 2nd rising edge (? ?) of bickb after the rising edge (? ?) of syncb. msb of sdtib is latched by the falling edge (? ?) of the bickb just after the output timing of sdtob?s msb. figure 86 1 1 msb of sdtob is output by the 2nd falling edge (? ?) of bickb after the rising edge (? ?) of syncb. msb of sdtib is latched by the rising edge (? ?) of the bickb just after the output timing of sdtob?s msb. figure 87 table 87. pcm i/f b format in mode 0 msbsa bckpa data interface format figure 0 0 msb of sdtoa is output by the rising edge (? ?) of synca. msb of sdtia is latched by the falling edge (? ?) of the bicka just after the output timing of sdtoa?s msb. figure 88 0 1 msb of sdtoa is output by the rising edge (? ?) of synca. msb of sdtia is latched by the rising edge (? ?) of the bicka just after the output timing of sdtoa?s msb. figure 89 1 0 msb of sdtoa is output by the rising edge (? ?) of the first bicka after the rising edge (? ?) of synca. msb of sdtia is latched by the falling edge (? ?) of the bicka just after the output timing of sdtoa?s msb. figure 90 1 1 msb of sdtoa is output by the falling edge (? ?) of the first bicka after the rising edge (? ?) of synca. msb of sdtia is latched by the rising edge (? ?) of the bicka just after the output timing of sdtoa?s msb. figure 91 table 88. pcm i/f a format in mode 1 msbsb bckpb data interface format figure 0 0 msb of sdtob is output by the rising edge (? ?) of syncb. msb of sdtib is latched by the falling edge (? ?) of the bickb just after the output timing of sdtob?s msb. figure 88 0 1 msb of sdtob is output by the rising edge (? ?) of syncb. msb of sdtib is latched by the rising edge (? ?) of the bickb just after the output timing of sdtob?s msb. figure 89 1 0 msb of sdtob is output by the rising edge (? ?) of the first bickb after the rising edge (? ?) of syncb. msb of sdtib is latched by the falling edge (? ?) of the bickb just after the output timing of sdtob?s msb. figure 90 1 1 msb of sdtob is output by the falling edge (? ?) of the first bickb after the rising edge (? ?) of syncb. msb of sdtib is latched by the rising edge (? ?) of the bickb just after the output timing of sdtob?s msb. figure 91 table 89. pcm i/f b format in mode 1
[ak4671] ms0666-e-02 2010/06 - 105 - sdtia sdtoa bic ka synca d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d on?t care don?t care d15 d14 d15 d14 1/fs2 d15 d14 d15 d14 (16bit linear) sdtia sdtoa d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don?t care don?t care d7 d6 d7 d6 (8 bit a -l aw/ -l aw) don?t care figure 84. timing of short frame sync (msbsa bit = ?0?, bckpa bit = ?0?) sdtia sdtoa bic ka synca d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d on?t care don?t care d15 d14 d15 d14 1/fs2 d15 d14 d15 d14 (16bit linear) sdtia sdtoa d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don?t care d on?t care d7 d6 d7 d6 (8 bit a -l aw/ -l aw) figure 85. timing of short frame sync (msbsa bit = ?0?, bckpa bit = ?1?) sdtia sdtoa bic ka synca d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d on?t care don?t care d15 d14 d15 d14 1/fs2 d15 d14 d15 d14 (16bit linear) sdtia sdtoa d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don?t care d on?t care d7 d6 d7 d6 (8 bit a -l aw/ -l aw) figure 86. timing of short frame sync (msbsa bit = ?1?, bckpa bit = ?0?)
[ak4671] ms0666-e-02 2010/06 - 106 - sdtia sdtoa bic ka synca d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d on?t care d15 d14 d15 d14 1/fs2 d15 d14 d15 d14 (16bit linear) sdtia sdtoa d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don?t care d on?t care d7 d6 d7 d6 (8 bit a -l aw/ -l aw) don?t care don?t care figure 87. timing of short frame sync (msbsa bit = ?1?, bckpa bit = ?1?) sdtia sdtoa bicka synca d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 don?t care d15 d14 d15 d14 1/fs2 d13 d13 d15 d14 d15 d14 (16bit linear) sdtia sdtoa d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don?t care don?t care d6 d5 d6 d5 (8 bit a -l aw/ -l aw) d7 d7 don?t care figure 88. timing of long frame sync (msbsa bit = ?0?, bckpa bit = ?0?) sdtia sdtoa bicka d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 don?t care d15 d14 d15 d14 d13 d13 d15 d14 d15 d14 (16bit linear) sdtia sdtoa d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don?t care don?t care d6 d5 d6 d5 (8 bit a -l aw/ -l aw) d7 d7 synca 1/fs2 don?t care figure 89. timing of long frame sync (msbsa bit = ?0?, bckpa bit = ?1?)
[ak4671] ms0666-e-02 2010/06 - 107 - sdtia sdtoa bicka d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 don?t care d15 d14 d15 d14 d13 d13 d15 d14 d15 d14 (16bit linear) sdtia sdtoa d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don?t care don?t care d6 d5 d6 d5 (8 bit a -l aw/ -l aw) d7 d7 synca 1/fs2 d on?t care don?t care figure 90. timing of long frame sync (msbsa bit = ?1?, bckpa bit = ?0?) sdtia sdtoa bicka d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 don?t care d15 d14 d15 d14 d13 d13 d15 d14 d15 d14 (16bit linear) sdtia sdtoa d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don?t care don?t care d6 d5 d6 d5 (8 bit a -l aw/ -l aw) d7 d7 synca (s la ve ) 1/fs2 don?t c are don?t care figure 91. timing of long frame sync (msbsa bit = ?1?, bckpa bit = ?1?)
[ak4671] ms0666-e-02 2010/06 - 108 - synca bicka (32fs2) sdtoa(o) sdtia(i) 0 15 14 15 14 110 13 13 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 1 0 15 15 10 9 1112131415 bicka (64fs2) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdtoa(o) sdtia(i) 15 14 13 don't care 1 15 15 0 15 14 15 don't care 15:msb, 0:lsb 13 10 15 don't care don't care figure 92. timing of msb justified synca bicka (32fs2) sdtoa(o) sdtia(i) 0 15 14 15 14 110 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 1 0 10 9 1112131415 bicka (64fs2) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdtoa(o) sdtia(i) 15 14 don't care 2 15 1 15 15 don't care 15:msb, 0:lsb 14 21 8 8 0 0 don't care figure 93. timing of i 2 s
[ak4671] ms0666-e-02 2010/06 - 109 - phone path mic-amp & alc receiver headphone speake r mic cpu tx rx baseband b/t phone call tx phone call tx recording phone call side tone phone call rx phone call rx recording sdto lch sdti lch sdtoa sdtia sdtob sdtib a/d stereo separation d/a m i x alc 5-band notch datt smute lpf hpf src-a src-b datt-c datt-b svolb hpf mix svola 5-band eq s e l bivol sdto rch sdti rch a udio i/f pcm i/f a pcm i/f b figure 94. internal mic/spk or external mic/hp phone call & recoring
[ak4671] ms0666-e-02 2010/06 - 110 - mic-amp & alc receiver headphone speake r mic cpu tx rx baseband b/t phone call tx phone call tx recording phone call side tone phone call rx phone call rx recording sdto lch sdti lch sdtoa sdtia sdtob sdtib a/d stereo separation d/a m i x alc 5-band notch datt smute lpf hpf src-a src-b datt-c datt-b svolb hpf mix svola 5-band eq s e l bivol sdto rch sdti rch a udio i/f pcm i/f a pcm i/f b figure 95. b/t headset phone call & recording
[ak4671] ms0666-e-02 2010/06 - 111 - general purpose output ak4671 supports general purpose output pin (g po) to control the external component. in the case of gpom1 bit = ?0?, gpo1 pin goes to ?h? at gpoe1 bit = ?1?. gpoe1 bit gpo1 pin 0 l (default) 1 h table 90. general purpose output 1 pin control (at gpom1 bit = ?0?) in the case of gpom1 bit = ?1?, gpo1 pi n goes to ?h? if the input level of the channel selected by a0 bit (sain1 or sain2 pin) is higher than the reference voltage that is i nput to the sain3 pin. in the case of gpom1 bit = ?1?, the reference voltage input to sain3 pi n should be lower than 0.5 x savdd. sain1/2 pin gpo1 pin < sain3 pin l (default) sain3 pin h table 91. general purpose output 1 pin control (at gpom1 bit = ?1?) in the case of gpom2 bit = ?0?, gpo2 pin goes to ?h? at gpoe2 bit = ?0?. gpoe2 bit gpo2 pin 0 l (default) 1 h table 92. general purpose output 2 pin control (at gpom2 bit = ?0?) in the case of gpom2 bit = ?1?, gpo2 pin outputs the mic detection result. ( table 21 ) input level of mdt pin gpo2 pin dtmic bit result 0.075 x avdd h 1 mic (headset) < 0.050 x avdd l 0 no mic (headphone) table 21. microphone detection result
[ak4671] ms0666-e-02 2010/06 - 112 - sar 10bit adc the ak4671 incorporates a 10-bit successive approximati on resistor a/d converter for dc measurement. the a/d converter output is a strai ght binary format as shown in table 93 : input voltage output code (avdd ? 1.5lsb) ~ avdd 3ffh (avdd ? 2.5lsb) ~ (avdd ? 1.5lsb) 3feh : : 0.5lsb ~ 1.5lsb 001h 0 ~ 0.5lsb 000h table 93. output code when pmsad bit is set to ?1?, 10bit adc is powered-up. when the control regist er is read, a/d conversion is executed and data is output. in case of 4-wire se rial control mode, 10bit a/d data is out put from 9th to 18th cclk clock when 4th bit is set to ?1? just after r/w bit. 10bit adc supports 3 kinds of analog input. a1 -0 bits select the measurement modes. mode a1 a0 input channel 0 0 0 sain1 (default) 1 0 1 sain2 2 1 0 sain3 3 1 1 n/a table 94. sar adc measurement mode (n/a: not available)
[ak4671] ms0666-e-02 2010/06 - 113 - [4-wire serial mode] (1) select the measurement mode by a1-0 bits and set pmsad bit = ?1? to power-up sar adc. (2) input ?1? at the 4th bit just after r/w bit so that a/d c onversion is executed and 10bit a/ d data is output from 9th to 18th cclk clock. [i 2 c mode] (1) select the measurement mode by a1-0 bits and set pmsad bit = ?1? to power-up sar adc. (2) read addr=5bh so that a/d conversion is executed and msb 8bit data is output. (3) continuously read addr=5ch then lsb 2bit data is output. [4-wire serial mode] (1) gpom1 bit should be set to ?1?. the gpo1 pi n can be used as the interrupt output pin. (2) select the measurement mode by a0 bit. (3) the gpo1 pin goes to ?h? when the input dc voltage of sain 1 or sain2 pin (selected by a0 bit) is higher than the input voltage of sain3 pin. (4) after cpu detects gpo1 pin = ?h?, set gpom1 b it = ?0? and pmsad bit = ?1? to power-up sar adc. (5) input ?1? at the 4th bit just after r/w bit so that a/d c onversion is executed and 10bit a/ d data is output from 9th to 18th cclk clock. [i 2 c mode] (1) gpom1 bit should be set to ?1?. the gpo1 pi n can be used as the interrupt output pin. (2) select the measurement mode by a0 bit. (3) the gpo1 pin goes to ?h? when the input dc voltage of sain 1 or sain2 pin (selected by a0 bit) is higher than the input voltage of sain3 pin. (4) after cpu detects gpo1 pin = ?h?, set gpom1 b it = ?0? and pmsad bit = ?1? to power-up sar adc. (5) read addr=5bh so that a/d conversion is executed and msb 8bit data is output. (6) continuously read addr=5ch then lsb 2bit data is output.
[ak4671] ms0666-e-02 2010/06 - 114 - serial control interface (1) 4-wire serial control mode (i2c pin = ?l?) internal registers may be written by using the 4-wire p interface pins (csn, cclk, cdti and cdto). in case except for 10bit sar adc data read, the data on this interface consists of a 3-bit chip address (fixed to ?100?), read/write (1bit), register addr ess (msb first, 7bits) and control data (msb first, 8bits). in case of 10bit sar adc data read, the data on this inte rface consists of a 3-bit chip address (fixed to ?101?), read/write (1bit: fixed to ?0?) and sar adc data (msb first, 10bits). address and data is clocked in on the ri sing edge of cclk and data is clocked out on the falling edge. address and data are latched on the 24th cclk rising edge (? ?) after csn falling edge (? ?) for write operations and cdto bit goes to hi-z after csn rising edge (? ?). csn should be set to ?h? once after 24th cclk for each address. the clock speed of cclk is 5mhz (max). the value of internal registers is initialized at pdn pin = ?l?. cdti cclk csn c2 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 d4 d5 d6 d7 0 0 0 c0 r/w c1 0 d0 d1 d2 d3 cdto hi-z write cdti c2 d4 d5 d6 d7 0 0 0 c0 r/w c1 0 d0 d1 d2 d3 cdto hi-z read (except for 10bit sar adc data) d4 d5 d6 d7 d0 d1 d2 d3 hi-z 0 8 9 101112131415 a1 a2 a3 a4 a5 a6 a0 0 a1 a2 a3 a4 a5 a6 a0 clock, "h" or "l" clock, "h" or "l" "h" or "l" "h" or "l" "h" or "l" "h" or "l" c2-c0: chip address (fixed to ?100?) r/w: read/write (0: read, 1: write) a6-a0: register address d7-d0: control data figure 96. serial control i/f timi ng (except for 10bit sar adc data) cclk csn 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 8 9 101112131415 cdti c2 d4 d5 d6 d7 0 0 0 c0 r/w c1 0 d0 d1 d2 d3 cdto hi-z read (10bit sar adc data) 0 0 d0 d1 0 0 0 0 hi-z d6 d7 d8 d9 d2 d3 d4 d5 clock, "h" or "l" "h" or "l" clock, "h" or "l" "h" or "l" c2-c0: chip address (fixed to ?101?) r/w: read/write (fixed to ?0?: read only) d9-d0: sar adc data figure 97. serial control i/ f timing (10bit sar adc data)
[ak4671] ms0666-e-02 2010/06 - 115 - (2) i 2 c-bus control mode (i2c pin = ?h?) the ak4671 supports the fast-mode i 2 c-bus (max: 400khz). pull-up resistors at sda and scl pins should be connected to (dvdd+0.3)v or less voltage. (2)-1. write operations figure 98 shows the data transfer sequence for the i 2 c-bus mode. all commands are pr eceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 105 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant six bits of the slave address are fixed as ?001001?. the next bit is cad0 (device address bit). this bit identifies the specific device on the bus. the hard-wired input pin (cad0 pin) sets these device address bits ( figure 99 ). if the slave address matches that of the ak4671, the ak4671 generates an acknow ledge and the operation is executed. the master must generate the acknowledge-relate d clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 106 ). a r/w bit value of ?1? indicates that th e read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the ak4671. the format is msb first, and the most significant 1-bit is fixed to ?0? ( figure 100 ). the data after the second byte contains c ontrol data. the format is msb first, 8bits ( figure 101 ). the ak4671 generates an acknowledge after each byte is received. a data transfer is always terminated by a stop condition generated by the master. a low to hi gh transition on the sda line while scl is high defines a stop condition ( figure 105 ). the ak4671 can perform more than one by te write operation per sequence. after receipt of the third byte the ak4671 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next addr ess. if the address exceeds 5ah prior to generating a stop condition, the address counter will ?roll over? to 00h and th e previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the cloc k signal on the scl line is low ( figure 107 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 98. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 1 cad0 r/w (the cad0 should match with cad0 pin.) figure 99. the first byte 0 a6 a5 a4 a3 a2 a1 a0 figure 100. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 101. byte structure after the second byte
[ak4671] ms0666-e-02 2010/06 - 116 - (2)-2. read operations set the r/w bit = ?1? for the read operation of the ak4671. af ter transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cy cle after the receipt of the first data word. after receiving each data packet the inte rnal 7-bit address counter is increm ented by one, and the next data is automatically taken into the next address. if the address exceeds 5ah prior to generating a stop condition, the address counter will ?roll over? to 00h and the data of 00h will be read out. the ak4671 supports two basic read operations: current address read and random address read. (2)-2-1. current address read (except for 10bit sar adc data) the ak4671 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the ak4671 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master doe s not generate an acknowledge but inst ead generates a stop condition, the ak4671 ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) n a c k p s t o p data(n) m a s t e r m a s t e r m a s t e r m a s t e r m a s t e r figure 102. current address read (2)-2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit ?1?, the mast er must first perform a ?dummy? write operation. the master issues a start request, a slave address (r/w bit = ?0?) and then the re gister address to read. after the regist er address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit ?1?. the ak4671 then generates an acknowledge, 1 byte of data and increments the internal a ddress counter by 1. if the ma ster does not generate an acknowledge but instead generates a stop condition, the ak4671 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k n a c k m a s t e r m a s t e r m a s t e r m a s t e r figure 103. random address read (except for 10bit sar adc data) when sar adc data is read, 5bh should be set as regist er address and 2 byte data should be read by random address read, then stop condition should be input. a/d readout format is msb fi rst, 2 byte width. upper 10bits are valid on 2byte (16-bit), and lowe r 6bits are filled with zero. sda slave address s s t a r t r/w="0" a c k a c k a c k data(d9-2) a c k data(d1-0) p s t o p sub address(5bh) s slave address r/w="1" s t a r t n a c k m a s t e r m a s t e r figure 104. random address read (10bit sar adc data)
[ak4671] ms0666-e-02 2010/06 - 117 - scl sda stop condition start condition s p figure 105. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 106. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 107. bit transfer on the i 2 c-bus
[ak4671] ms0666-e-02 2010/06 - 118 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h ad/da power manageme nt pmdar pmdal pmadr pmadl pmmicr pmmicl pmmp pmvcm 01h pll mode select 0 fs3 fs2 fs1 fs0 pll3 pll2 pll1 pll0 02h pll mode select 1 btclk lp bcko ps1 ps0 mcko m/s pmpll 03h format select 0 0 0 sdod msbs bckp dif1 dif0 04h mic signal select mdif4 mdif 3 mdif2 mdif1 inr1 inr0 inl1 inl0 05h mic amp gain mgnr3 mgnr2 mgnr1 mgnr0 mgnl3 mgnl2 mgnl1 mgnl0 06h mixing power management 0 0 0 0 0 0 dtmic pmloopr pmloopl 07h mixing power management pmainr4 pmainl4 pmainr3 pmainl3 pmainr2 pmainl2 pmainr1 pmainl1 08h output volume control hpg3 hpg2 hpg1 hpg0 0 l1vl2 l1vl1 l1vl0 09h lout1 signal select l1g1 l1g0 loopl linl4 linl3 linl2 linl1 dacl 0ah rout1 signal select l2g1 l2g0 loopr rinr4 rinr3 rinr2 rinr1 dacr 0bh lout2 signal select l3g1 l3g0 loophl linh4 linh3 linh2 linh1 dachl 0ch rout2 signal select l4g1 l4g0 loophr rinh4 rinh3 rinh2 rinh1 dachr 0dh lout3 signal select lpg1 lpg0 loopsl lins4 lins3 lins2 lins1 dacsl 0eh rout3 signal select 0 0 loopsr rins4 rins3 rins2 rins1 dacsr 0fh lout1 power manage ment 0 0 rcv loopm lom lops1 pmro1 pmlo1 10h lout2 power management 0 pmro2s pmlo2s loopm2 lom2 muten pmro2 pmlo2 11h lout3 power manage ment l3vl1 l3vl0 lodif loopm3 lom3 lops3 pmro3 pmlo3 12h lch input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 13h rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 14h alc reference select ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 15h digital mixing control srmxr1 srmxr0 srmxl1 srmxl0 pfmxr1 pfmxr0 pfmxl1 pfmxl0 16h alc timer select 0 rfst1 rfst0 wtm2 wtm1 wtm0 ztm1 ztm0 17h alc mode control 0 zelmn lmat1 lmat0 rgain1 rgain0 lmth1 lmth0 18h mode control 1 dam mixd sdim1 sdim0 eq adm ivolc alc 19h mode control 2 sra1 sra0 biv2 biv1 biv0 smute ovtm ovolc 1ah lch output volume control ovl7 ovl6 ovl5 ovl4 ovl3 ovl2 ovl1 ovl0 1bh rch output volume control ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 1ch side tone a control 0 0 svar2 svar1 svar0 sval2 sval1 sval0 1dh digital filter select gn1 gn0 lpf hpf eq0 fil3 0 pfsel 1eh fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 1fh fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 20h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 21h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 22h eq co-efficient 0 e0a7 e0a6 e0a5 e0a4 e0a3 e0a2 e0a1 e0a0 23h eq co-efficient 1 e0a15 e0a14 e0 a13 e0a12 e0a11 e0a10 e0a9 e0a8 24h eq co-efficient 2 e0b7 e0b6 e0b5 e0b4 e0b3 e0b2 e0b1 e0b0 25h eq co-efficient 3 0 0 e0b13 e0b12 e0b11 e0b10 e0b9 e0b8 26h eq co-efficient 4 e0c7 e0c6 e0c5 e0c4 e0c3 e0c2 e0c1 e0c0 27h eq co-efficient 5 e0c15 e0c14 e0c13 e0c12 e0c11 e0c10 e0c9 e0c8 28h fil1 co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 29h fil1 co-efficient 1 f1as 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 2ah fil1 co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 2bh fil1 co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 2ch fil2 co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 2dh fil2 co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 2eh fil2 co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 2fh fil2 co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8
[ak4671] ms0666-e-02 2010/06 - 119 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 31h reserved 0 0 0 0 0 0 0 0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1 a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2 a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3 a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4 a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 50h eq control 250hz/100hz eqb3 eqb2 eqb1 eqb0 eqa3 eqa2 eqa1 eqa0 51h eq control 3.5khz/1khz eqd3 eqd2 eqd1 eqd0 eqc3 eqc2 eqc1 eqc0 52h eq control 10khz 0 0 0 0 eqe3 eqe2 eqe1 eqe0 53h pcm i/f control 0 gpom2 gpoe2 pllbt2 pllbt1 pllbt0 pmpcm pmsrb pmsra 54h pcm i/f control 1 sdoad bcko2 msbsa bckpa lawa1 lawa0 fmta1 fmta0 55h pcm i/f control 2 sdobd pllbt3 msbsb bckpb lawb1 lawb0 fmtb1 fmtb0 56h digital volume b control bvl7 bvl6 bvl5 bvl4 bvl3 bvl2 bvl1 bvl0 57h digital volume c control cvl7 cvl6 cvl5 cvl4 cvl3 cvl2 cvl1 cvl0 58h side tone volume control 0 0 0 0 sdoa svb2 svb1 svb0 59h digital mixing control sdor1 s dor0 sdol1 sdol0 bvmx1 bvmx0 sbmx1 sbmx0 5ah sar adc control 0 0 0 gpom1 gpoe1 a1 a0 pmsad note 67. pdn pin = ?l? resets the registers to their default values. note 68. the bits defined as 0 must contain a ?0? value. note 69. addresses 1eh to 2fh and 32h to 4fh cannot be read.
[ak4671] ms0666-e-02 2010/06 - 120 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h ad/da power manageme nt pmdar pmdal pmadr pmadl pmmicr pmmicl pmmp pmvcm r/w r/w r/w r/w r/ w r/w r/w r/w r/w (default) 0 0 0 0 0 0 0 0 pmvcm: vcom power management 0: power down (default) 1: power up when any blocks are powered-up, th e pmvcm bit must be set to ?1?. pmvcm bit can be set to ?0? only when all power management bits are ?0?. pmmp: mpwr pin power management 0: power down: hi-z (default) 1: power up pmmicl: mic-amp lch power management 0: power down (default) 1: power up pmmicr: mic-amp rch power management 0: power down (default) 1: power up pmadl: adc lch power management 0: power down (default) 1: power up when the pmadl or pmadr bit is changed from ?0 ? to ?1?, the initialization cycle (1059/fs=24ms @44.1khz) starts. after initializing, digital data of the adc is output. pmadr: adc rch power management 0: power down (default) 1: power up pmdal: dac lch power management 0: power down (default) 1: power up pmdar: dac rch power management 0: power down (default) 1: power up each block can be powered-down respectivel y by writing ?0? in each bit of this a ddress. when the pdn pin is ?l?, all blocks are powered-down regardless of setting of this address. in this case, regist er is initialized to the default value. when all power management bits are ?0?, all blocks are powered-down. the register va lues remain unchanged. power supply current is 20 a(typ) in this case. for fully shut down (typ. 1 a), pdn pin should be ?l?. when neither adc nor dac are used, external clocks may not be present. when adc or dac is used, external clocks must always be present.
[ak4671] ms0666-e-02 2010/06 - 121 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h pll mode select 0 fs3 fs2 fs1 fs0 pll3 pll2 pll1 pll0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 1 1 1 0 1 1 0 pll3-0: pll reference clock select ( table 4 ) default: ?0110?(mcki pin, 12mhz) fs3-0: sampling frequency select ( table 5 and table 6 ) and mcki frequency select ( table 11) fs3-0 bits select sampling frequency at p ll mode and mcki frequency at ext mode. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h pll mode select 1 btclk lp bcko ps1 ps0 mcko m/s pmpll r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmpll: pll power management 0: ext mode and power down (default) 1: pll mode and power up m/s: master / slave mode select 0: slave mode (default) 1: master mode mcko: master clock output enable 0: disable: mcko pin = ?l? (default) 1: enable: output frequency is selected by ps1-0 bits. ps1-0: mcko output frequency select ( table 9 ) default: ?00?(256fs) bcko: bick output frequenc y select at master mode ( table 10 ) lp: low power mode 0: normal mode (default) 1: low power mode: available at fs=22.05khz or less. btclk: clock mode of audio codec 0: synchronized to audio i/f (default) 1: synchronized to pcm i/f btclk bit is enabled at only pmpll bit = ?0?. when btclk bit is ?1?, audio codec and the digital block (shown in figure 57 ) operate by the clock generated by pllbt.
[ak4671] ms0666-e-02 2010/06 - 122 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h format select 0 0 0 sdod msbs bckp dif1 dif0 r/w rd rd rd r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 dif1-0: audio interface format ( table 16 ) default: ?10? (left jutified) bckp: bick polarity at dsp mode ( table 17 ) ?0?: sdto is output by the rising edge (? ?) of bick and sdti is latched by the falling edge (? ?). (default) ?1?: sdto is output by the falling edge (? ?) of bick and sdti is latched by the rising edge (? ?). msbs: lrck phase at dsp mode ( table 17 ) ?0?: the rising edge (? ?) of lrck is half clock of bick before the channel change. (default) ?1?: the rising edge (? ?) of lrck is one clock of bick before the channel change. sdod: sdto disable ( table 47 ) ?0?: enable (default) ?1?: disable (?l?) addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mic signal select mdif4 mdif 3 mdif2 mdif1 inr1 inr0 inl1 inl0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 inl1-0: mic-amp lch input source select ( table 18 ) default: ?00? (lin1) inr1-0: mic-amp rch input source select ( table 18 ) default: ?00? (rin1) mdif1: line1 input type select 0: single-ended input (l in1/rin1 pins: default) 1: full-differential input (in1+/in1 ? pins) mdif2: line2 input type select 0: single-ended input (l in2/rin2 pins: default) 1: full-differential input (in2+/in2 ? pins) mdif3: line3 input type select 0: single-ended input (l in3/rin3 pins: default) 1: full-differential input (in3+/in3 ? pins) mdif4: line4 input type select 0: single-ended input (l in4/rin4 pins: default) 1: full-differential input (in4+/in4 ? pins)
[ak4671] ms0666-e-02 2010/06 - 123 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mic amp gain mgnr3 mgnr2 mgnr1 mgnr0 mgnl3 mgnl2 mgnl1 mgnl0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 1 0 1 0 1 0 1 mgnl3-0: mic-amp lch gain control ( table 19 ) default: ?0101? (0db) mgnr3-0: mic-amp rch gain control ( table 19 ) default: ?0101? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h mixing power management 0 0 0 0 0 0 dtmic pmloopr pmloopl r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 0 0 pmloopl: mic-amp lch mixing circuit power management 0: power down (default) 1: power up pmloopr: mic-amp rch mixing circuit power management 0: power down (default) 1: power up dtmic: microphone detection result (read only: table 21 ) 0: microphone is not detected. (default) 1: microphone is detected.
[ak4671] ms0666-e-02 2010/06 - 124 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h mixing power management 1 pmainr4 pmainl4 pmainr3 pmainl3 pmainr2 pmainl2 pmainr1 pmainl1 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmainl1: lin1 mixing circuit power management 0: power down (default) 1: power up pmainr1: rin1 mixing circuit power management 0: power down (default) 1: power up pmainl2: lin2 mixing circuit power management 0: power down (default) 1: power up pmainr2: rin2 mixing circuit power management 0: power down (default) 1: power up pmainl3: lin3 mixing circuit power management 0: power down (default) 1: power up pmainr3: rin3 mixing circuit power management 0: power down (default) 1: power up pmainl4: lin4 mixing circuit power management 0: power down (default) 1: power up pmainr4: rin4 mixing circuit power management 0: power down (default) 1: power up addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h output volume control hpg3 hpg2 hpg1 hpg0 0 l1vl2 l1vl1 l1vl0 r/w r/w r/w r/w r/ w rd r/w r/w r/w default 1 0 1 1 0 1 0 1 l1vl2-0: lout1/rout1 ou tput volume control ( table 67 ) default: ?5h? (0db) hpg3-0: lout2/rout2 out put volume control ( table 70 ) default: ?bh? (0db)
[ak4671] ms0666-e-02 2010/06 - 125 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h lout1 signal select l1g1 l1g0 loopl linl4 linl3 linl2 linl1 dacl r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dacl: switch control from dac lch to lout1 0: off (default) 1: on when pmlo1 bit is ?1?, dacl bit is enabled. when pmlo1 bit is ?0?, the lout1 pin goes to vss1. linl1: switch control from lin1 to lout1 0: off (default) 1: on linl2: switch control from lin2 to lout1 0: off (default) 1: on linl3: switch control from lin3 to lout1 0: off (default) 1: on linl4: switch control from lin4 to lout1 0: off (default) 1: on loopl: switch control from mic-amp lch to lout1 0: off (default) 1: on l1g1-0: lin1/rin1 mixing gain control ( table 60 ) default: ?00? (0db)
[ak4671] ms0666-e-02 2010/06 - 126 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah rout1 signal select l2g1 l2g0 loopr rinr4 rinr3 rinr2 rinr1 dacr r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dacr: switch control from dac rch to rout1 0: off (default) 1: on when pmro1 bit is ?1?, dacr bit is enabled. when pmro1 bit is ?0?, the rout1 pin goes to vss1. rinr1: switch control from rin1 to rout1 0: off (default) 1: on rinr2: switch control from rin2 to rout1 0: off (default) 1: on rinr3: switch control from rin3 to rout1 0: off (default) 1: on rinr4: switch control from rin4 to rout1 0: off (default) 1: on loopr: switch control from mic-amp rch to rout1 0: off (default) 1: on l2g1-0: lin2/rin2 mixing gain control ( table 61 ) default: ?00? (0db)
[ak4671] ms0666-e-02 2010/06 - 127 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh lout2 signal select l3g1 l3g0 loophl linh4 linh3 linh2 linh1 dachl r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dachl: switch control from dac lch to lout2 0: off (default) 1: on linh1: switch control from lin1 to lout2 0: off (default) 1: on linh2: switch control from lin2 to lout2 0: off (default) 1: on linh3: switch control from lin3 to lout2 0: off (default) 1: on linh4: switch control from lin4 to lout2 0: off (default) 1: on loophl: switch control from mic-amp lch to lout2 0: off (default) 1: on l3g1-0: lin3/rin3 mixing gain control ( table 62 ) default: ?00? (0db)
[ak4671] ms0666-e-02 2010/06 - 128 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch rout2 signal select l4g1 l4g0 loophr rinh4 rinh3 rinh2 rinh1 dachr r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dachr: switch control from dac rch to rout2 0: off (default) 1: on rinh1: switch control from rin1 to rout2 0: off (default) 1: on rinh2: switch control from rin2 to rout2 0: off (default) 1: on rinh3: switch control from rin3 to rout2 0: off (default) 1: on rinh4: switch control from rin4 to rout2 0: off (default) 1: on loophr: switch control from mic-amp rch to rout2 0: off (default) 1: on l4g1-0: lin4/rin4 mixing gain control ( table 63 ) default: ?00? (0db)
[ak4671] ms0666-e-02 2010/06 - 129 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh lout3 signal select lpg1 lpg0 loopsl lins4 lins3 lins2 lins1 dacsl r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dacsl: switch control from dac lch to lout3 0: off (default) 1: on when pmlo3 bit is ?1?, dacsl bit is enabled. wh en pmlo3 bit is ?0?, the lout3 pin goes to vss1. lins1: switch control from lin1 to lout3 0: off (default) 1: on lins2: switch control from lin2 to lout3 0: off (default) 1: on lins3: switch control from lin3 to lout3 0: off (default) 1: on lins4: switch control from lin4 to lout3 0: off (default) 1: on loopsl: switch control from mic-amp lch to lout3 0: off (default) 1: on lpg1-0: mic-amp mixing gain control ( table 64 ) default: ?00? (0db)
[ak4671] ms0666-e-02 2010/06 - 130 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh rout3 signal select 0 0 loopsr rins4 rins3 rins2 rins1 dacsr r/w rd rd r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dacsr: switch control from dac rch to rout3 0: off (default) 1: on when pmro3 bit is ?1?, dacr bit is enabled. when pmro3 bit is ?0?, the rout3 pin goes to vss1. rins1: switch control from rin1 to rout3 0: off (default) 1: on rins2: switch control from rin2 to rout3 0: off (default) 1: on rins3: switch control from rin3 to rout3 0: off (default) 1: on rins4: switch control from rin4 to rout3 0: off (default) 1: on loopsr: switch control from mic-amp rch to rout3 0: off (default) 1: on
[ak4671] ms0666-e-02 2010/06 - 131 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh lout1 power manage ment 0 0 rcv loopm lom lops1 pmro1 pmlo1 r/w rd rd r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmlo1: lout1 power management 0: power down (default) 1: power up pmro1: rout1 power management 0: power down (default) 1: power up lops1: lout1/rout1 power save mode 0: normal operation (default) 1: power save mode lom: mono mixing from dac to lout1/rout1 0: stereo mixing (default) 1: mono mixing loopm: mono mixing from mic-amp to lout1/rout1 0: stereo mixing (default) 1: mono mixing rcv: receiver select 0: stereo line output (l out1/rout1 pins) (default) 1: mono receiver out put (rcp/rcn pins)
[ak4671] ms0666-e-02 2010/06 - 132 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h lout2 power management 0 pmro2s pmlo2s loopm2 lom2 muten pmro2 pmlo2 r/w rd r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmlo2: lout2 power management 0: power down (default) 1: power up pmro2: rout2 power management 0: power down (default) 1: power up muten: lout2/rout2 mute control 0: mute (default) 1: normal operation lom2: mono mixing from dac to lout2/rout2 0: stereo mixing (default) 1: mono mixing loopm2: mono mixing from mic-amp to lout2/rout2 0: stereo mixing (default) 1: mono mixing pmlo2s: lout2 mix-amp power management 0: power down (default) 1: power up pmro2s: rout2 mix-amp power management 0: power down (default) 1: power up
[ak4671] ms0666-e-02 2010/06 - 133 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h lout3 power mana gement l3vl1 l3vl0 lodif loopm3 lom3 lops3 pmro3 pmlo3 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 0 0 0 0 0 0 0 pmlo3: lout3 power management 0: power down (default) 1: power up pmro3: rout3 power management 0: power down (default) 1: power up lops3: lout3/rout3 power save mode 0: normal operation (default) 1: power save mode lom3: mono mixing from dac to lout3/rout3 0: stereo mixing (default) 1: mono mixing loopm3: mono mixing from mic-amp to lout3/rout3 0: stereo mixing (default) 1: mono mixing lodif: lineout select 0: single-ended stereo line out put (lout3/rout3 pins) (default) 1: full-differential mono li ne output (lop/lon pins) l3vl1-0: lout3/rout3 ou tput gain control ( table 73 ) default: ?10? (0db)
[ak4671] ms0666-e-02 2010/06 - 134 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h lch input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 13h rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 0 0 1 0 0 0 1 ivl7-0, ivr7-0: input digital volume; 0.375db step, 242 level ( table 33 ) default: ?91h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 14h alc reference select ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 1 1 0 0 0 0 1 ref7-0: reference value at alc recovery op eration (recording); 0.375db step, 242 level ( table 29 ) default: ?e1h? (+30.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 15h digital mixing control srmxr1 srmxr0 srmxl1 srmxl0 pfmxr1 pfmxr0 pfmxl1 pfmxl0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pfmxl1-0: 5-band eq lch input mixing 1 ( table 49 ) default: ?00? (sdti) pfmxr1-0: 5-band eq rch input mixing 1 ( table 50 ) default: ?00? (sdti) srmxl1-0: 5-band eq lch input mixing 2 ( table 51 ) default: ?00? (sdti) srmxr1-0: 5-band eq rch input mixing 2 ( table 52 ) default: ?00? (sdti) addr register name d7 d6 d5 d4 d3 d2 d1 d0 16h alc timer select 0 rfst 1 rfst0 wtm2 wtm1 wtm0 ztm1 ztm0 r/w rd r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 ztm1-0: alc limiter/recovery opera tion zero crossing timeout period ( table 26 ) default: ?00? (128/fs) wtm2-0: alc recovery waiting period ( table 27 ) default: ?000? (128/fs) rfst1-0: alc first recovery speed ( table 30 ) default: ?00? (4times)
[ak4671] ms0666-e-02 2010/06 - 135 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 17h alc mode control 0 zelmn lmat1 lmat0 rgain1 rgain0 lmth1 lmth0 r/w rd r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 lmth1-0: alc limiter detection leve l / recovery counter reset level ( table 24 ) default: ?00? rgain1-0: alc recovery gain step ( table 28 ) default: ?00? lmat1-0: alc limiter att step ( table 25 ) default: ?00? zelmn: zero crossing detection en able at alc limiter operation 0: enable (default) 1: disable addr register name d7 d6 d5 d4 d3 d2 d1 d0 18h mode control 1 dam mixd sdim1 sdim0 eq adm ivolc alc r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 alc: alc enable 0: alc disable (default) 1: alc enable ivolc: input digital volume control mode select 0: independent 1: dependent (default) when ivolc bit = ?1?, ivl7-0 bits control both lch a nd rch volume level, while register values of ivl7-0 bits are not written to ivr7-0 bits. when ivolc bit = ?0?, iv l7-0 bits control lch level and ivr7-0 bits control rch level, respectively. adm: mono recording ( table 44 ) 0: stereo (default) 1: mono: (l+r)/2 eq: select 5-band equalizer 0: off (default) 1: on sdim1-0: sdti input signal select ( table 48 ) default: ?00? (l=lch, r=rch) mixd: dac and src-a mono mixing ( table 53 and table 54 ) 0: l+r (default) 1: (l+r)/2 dam: dac mono mixing ( table 53 ) 0: stereo (default) 1: mono: (l+r) or (l+r)/2 is selected by mixd bit.
[ak4671] ms0666-e-02 2010/06 - 136 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 19h mode control 2 sra1 sra0 biv2 biv1 biv0 smute ovtm ovolc r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 ovolc: output digital volu me control mode select 0: independent 1: dependent (default) when ovolc bit = ?1?, ovl7-0 bits control both lch and rch volume level, while register values of ovl7-0 bits are not written to ovr7-0 bits. when ovol c bit = ?0?, ovl7-0 bits control lch level and ovr7-0 bits control rch level, respectively. ovtm: digital volume transition time setting 0: 1061/fs (default) 1: 256/fs this is the transition time between ovl/r7-0 bits = 00h and ffh. smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted biv2-0: sdtib input volume control ( table 41 ) default: ?0h? (0db) sra1-0: src-a input signal select ( table 54 ) default: ?00? (lch) addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ah lch output volume control ovl7 ovl6 ovl5 ovl4 ovl3 ovl2 ovl1 ovl0 1bh rch output volume control ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 1 1 0 0 0 ovl7-0, ovr7-0: output digital volume ( table 36 ) default: ?18h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ch side tone a control 0 0 svar2 svar1 svar0 sval2 sval1 sval0 r/w rd rd r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 sval2-0, svar2-0: side tone volume a (svola) ( table 34 ) default: ?000? (0db)
[ak4671] ms0666-e-02 2010/06 - 137 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 1dh digital filter select gn1 gn0 lpf hpf eq0 fil3 hpfad pfsel r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 pfsel : signal select of programmable filter block ( table 43 ) 0: adc output data (default) 1: sdti input data hpfad: hpf control of adc 0: off 1: on (default) when hpfad bit is ?1?, the settings of f1a13-0 and f1b13-0 bits are enabled. when hpfad bit is ?0?, hpfad block is through (0db). gn1-0: gain select at gain block ( table 23 ) default: ?00? (0db) fil3: fil3 (stereo separation emphasi s filter) coefficient setting enable 0: disable (default) 1: enable when fil3 bit is ?1?, the settings of f3a13-0 and f3b13- 0 bits are enabled. when fi l3 bit is ?0?, fil3 block is off (mute). eq0: eq0 (gain compensation f ilter) coefficient setting enable 0: disable (default) 1: enable when eq0 bit is ?1?, the settings of e0a15-0, e0b13-0 and e0c15-0 bits are enable d. when eq0 bit is ?0?, eq0 block is through (0db). hpf: hpf coefficient setting enable 0: disable (default) 1: enable when hpf bit is ?1?, the settings of f1a13-0 and f1b13- 0 bits are enabled. when hpf bit is ?0?, hpf block is through (0db). lpf: lpf coefficient setting enable 0: disable (default) 1: enable when lpf bit is ?1?, the settings of f2a13-0 and f2b13- 0 bits are enabled. when lpf bit is ?0?, lpf block is through (0db).
[ak4671] ms0666-e-02 2010/06 - 138 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 1eh fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 1fh fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 20h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 21h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 22h eq co-efficient 0 e0a7 e0a6 e0a5 e0a4 e0a3 e0a2 e0a1 e0a0 23h eq co-efficient 1 e0a15 e0a14 e0a13 e0a12 e0a11 e0a10 e0a9 e0a8 24h eq co-efficient 2 e0b7 e0b6 e0b5 e0b4 e0b3 e0b2 e0b1 e0b0 25h eq co-efficient 3 0 0 e0b13 e0b12 e0b11 e0b10 e0b9 e0b8 26h eq co-efficient 4 e0c7 e0c6 e0c5 e0c4 e0c3 e0c2 e0c1 e0c0 27h eq co-efficient 5 e0c15 e0c14 e0c13 e0c12 e0c11 e0c10 e0c9 e0c8 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 f3a13-0, f3b13-0: fil3 (stereo separati on emphasis filter) coefficient (14bit x 2) default: ?0000h? f3as: fil3 (stereo separation emphasis filter) select 0: hpf (default) 1: lpf e0a15-0, e0b13-0, e0c15-c0: eq0 (gain compen sation filter) coefficient (14bit x 2 + 16bit x 1) default: ?0000h? addr register name d7 d6 d5 d4 d3 d2 d1 d0 28h fil1 co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 29h fil1 co-efficient 1 0 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 2ah fil1 co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 2bh fil1 co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 r/w w w w w w w w w default f1a13-0 bits = ?1fa9h?, f1b13-0 bits = ?20adh? f1a13-0, f1b13-b0: fil1 (wind-noise reduction filter) coefficient (14bit x 2) default: f1a13-0 bits = ?1fa9h?, f1b13- 0 bits = ?20adh? (fc=150hz@fs=44.1khz) addr register name d7 d6 d5 d4 d3 d2 d1 d0 2ch fil2 co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 2dh fil2 co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 2eh fil2 co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 2fh fil2 co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 f2a13-0, f2b13-b0: fil2 (lpf) coefficient (14bit x 2) default: ?0000h?
[ak4671] ms0666-e-02 2010/06 - 139 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 r/w rd rd rd r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 eq1: equalizer 1 coefficient setting enable 0: disable (default) 1: enable when eq1 bit is ?1?, the settings of e1a15-0, e1b15-0 and e1c15-0 bits are enable d. when eq1 bit is ?0?, eq1 block is through (0db). eq2: equalizer 2 coefficient setting enable 0: disable (default) 1: enable when eq2 bit is ?1?, the settings of e2a15-0, e2b15-0 and e2c15-0 bits are enable d. when eq2 bit is ?0?, eq2 block is through (0db). eq3: equalizer 3 coefficient setting enable 0: disable (default) 1: enable when eq3 bit is ?1?, the settings of e3a15-0, e3b15-0 and e3c15-0 bits are enable d. when eq3 bit is ?0?, eq3 block is through (0db). eq4: equalizer 4 coefficient setting enable 0: disable (default) 1: enable when eq4 bit is ?1?, the settings of e4a15-0, e4b15-0 and e4c15-0 bits are enable d. when eq4 bit is ?0?, eq4 block is through (0db). eq5: equalizer 5 coefficient setting enable 0: disable (default) 1: enable when eq5 bit is ?1?, the settings of e5a15-0, e5b15-0 and e5c15-0 bits are enable d. when eq5 bit is ?0?, eq5 block is through (0db).
[ak4671] ms0666-e-02 2010/06 - 140 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 e1a15-0, e1b15-0, e1c15-0: equalizer 1 coefficient (16bit x3) default: ? 0000h ? e2a15-0, e2b15-0, e2c15-0: equalizer 2 coefficient (16bit x3) default: ? 0000h ? e3a15-0, e3b15-0, e3c15-0: equalizer 3 coefficient (16bit x3) default: ? 0000h ? e4a15-0, e4b15-0, e4c15-0: equalizer 4 coefficient (16bit x3) default: ? 0000h ? e5a15-0, e5b15-0, e5c15-0: equalizer 5 coefficient (16bit x3) default: ? 0000h ?
[ak4671] ms0666-e-02 2010/06 - 141 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 50h eq control 250hz/100hz eqb3 eqb2 eqb1 eqb0 eqa3 eqa2 eqa1 eqa0 51h eq control 3.5khz/1khz eqd3 eqd2 eqd1 eqd0 eqc3 eqc2 eqc1 eqc0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 0 0 0 1 0 0 0 addr register name d7 d6 d5 d4 d3 d2 d1 d0 52h eq control 10khz 0 0 0 0 eqe3 eqe2 eqe1 eqe0 r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 1 0 0 0 eqa3-0: select the boost level of 100hz eqb3-0: select the boost level of 250hz eqc3-0: select the boost level of 1khz eqd3-0: select the boost level of 3.5khz eqe3-0: select the boost level of 10khz see table 35 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 53h pcm i/f control 0 gpom2 gpoe2 pllbt2 pllbt1 pllbt0 pmpcm pmsrb pmsra r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmsra: src-a power management 0: power down (default) 1: power up pmsrb: src-b power management 0: power down (default) 1: power up pmpcm: pcm i/f power management 0: power down (default) 1: power up pllbt2-0: pllbt reference clock select ( table 76 ) pllbt3 bit is d6 of addr=55h. default: ?0000?: synca gpoe2: general purpose output 2 enable at gpom2 bit = ?1? ?0?: gpo2 pin = ?l? (default) ?1?: gpo2 pin = ?h? gpom2: general purpose ou tput 2 operation mode ( table 92 ) ?0?: controlled by gpoe2 bit (default) ?1?: mic detection interrupt
[ak4671] ms0666-e-02 2010/06 - 142 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 54h pcm i/f control 2 sdoad bcko2 msbsa bckpa lawa1 lawa0 fmta1 fmta0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 fmta1-0: pcm i/f a format ( table 84 ) default: ?00? (mode 0) lawa1-0: pcm i/f a mode ( table 82 ) default: ?00? (mode 0) bckpa: bicka polarity of pcm i/f a ( table 86 ) ?0?: sdtoa is output by the rising edge (? ?) of bicka and sdtia is latched by the falling edge (? ?). (default) ?1?: sdtoa is output by the falling edge (? ?) of bicka and sdtia is latched by the rising edge (? ?). msbsa: synca phase of pcm i/f a ( table 86 ) ?0?: the rising edge (? ?) of synca is half clock of bicka before the channel change. (default) ?1?: the rising edge (? ?) of synca is one clock of bicka before the channel change. bcko2: bicka/b output frequenc y select at master mode ( table 77 ) 0: 16fs2 (default) 1: 32fs2 sdoad: sdtoa disable ( table 56 ) ?0?: enable (default) ?1?: disable (?l?) addr register name d7 d6 d5 d4 d3 d2 d1 d0 55h pcm i/f control 3 sdobd pllbt3 msbsb bckpb lawb1 lawb0 fmtb1 fmtb0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 fmtb1-0: pcm i/f b format ( table 85 ) default: ?00? (mode 0) lawb1-0: pcm i/f b mode ( table 83 ) default: ?00? (mode 0) bckpb: bickb polarity of pcm i/f b ( table 87 ) ?0?: sdtob is output by the rising edge (? ?) of bickb and sdtib is latched by the falling edge (? ?). (default) ?1?: sdtob is output by the falling edge (? ?) of bickb and sdtib is latched by the rising edge (? ?). msbsb: syncb phase of pcm i/f b ( table 87 ) ?0?: the rising edge (? ?) of syncb is half clock of bickb before the channel change. (default) ?1?: the rising edge (? ?) of syncb is one clock of bickb before the channel change. pllbt3: pllbt reference clock select ( table 76 ) pllbt2-0 bits is d5-3 of addr=53h. default: ?0000?: synca sdobd: sdtob disable ( table 58 ) ?0?: enable (default) ?1?: disable (?l?)
[ak4671] ms0666-e-02 2010/06 - 143 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 56h digital volume b control bvl7 bv l6 bvl5 bvl4 bvl3 bvl2 bvl1 bvl0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 1 1 0 0 0 bvl7-0: digital volume b ( table 38 ) default: ?18h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 57h digital volume c control cvl7 cv l6 cvl5 cvl4 cvl3 cvl2 cvl1 cvl0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 1 1 0 0 0 cvl7-0: digital volume c ( table 39 ) default: ?18h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 58h side tone volume control 0 0 0 0 sdoa svb2 svb1 svb0 r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 svb2-0: side tone volume ( table 40 ) default: ?0h? (0db) sdoa: sdtoa output signal select ( table 55 ) ?0?: src-a (default) ?1?: sdti-b addr register name d7 d6 d5 d4 d3 d2 d1 d0 59h digital mixing control sdor1 s dor0 sdol1 sdol0 bvmx1 bvmx0 sbmx1 sbmx0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 sbmx1-0: sdtob output signal select ( table 57 ) default: ?00? (sdtia) bvmx1-0: src-b input signal select ( table 59 ) default: ?00? (sdtia) sdol1-0: sdto lch output mixing ( table 45 ) default: ?00? (lch signal selected by table 44 ) sdor1-0: sdto rch output mixing ( table 46 ) default: ?00? (rch signal selected by table 44 )
[ak4671] ms0666-e-02 2010/06 - 144 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 5ah sar adc control 0 0 0 gpom1 gpoe1 a1 a0 pmsad r/w rd rd rd r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmsad: 10bit adc power management ?0?: power down (default) ?1?: power up a1-0: sar adc measurement mode ( table 94 ) default: ?00? (ain1) gpoe1: general purpose output 1 enable at gpom1 bit = ?1? ?0?: gpo pin = ?l? (default) ?1?: gpo pin = ?h? gpom1: general purpose ou tput 1 operation mode ?0?: controlled by gpoe bit (default) ?1?: controlled by a0 bit
[ak4671] ms0666-e-02 2010/06 - 145 - system design figure 108 shows the system connection diagram for the ak4671. the evaluation board [akd4671] demonstrates the optimum layout, power supply arra ngements and measurement results. test lout2 rout2 vcom vcocbt vss2 sdtoa synca gpo2 avdd vss1 mutet vcoc pvdd tvdd2 bicka cdti sdtia rcp rcn vss4 dvdd rout3 lout3 cclk csn rin4 lin4 i2c bick lin3 rin3 mcki mcko in2+ in2 ? pdn lrck in1+ in1 ? sain2 savdd tvdd3 sdtob bickb sdto cdto mdt mpwr sain3 sain1 vss3 syncb sdtib sdti gpo1 nc ak4671eg analog 2.2 3.6v 1u rp cp 0.1u 2.2u r c headphone 0.1u 0.1u base band digital (base band) 1.6 3.6v p digital ( p & cpu) 1.6 3.6v cpu bluetooth module digital (bluetooth) 1.6 3.6v 0.1u 0.1u 0.1u 0.1u 1 k 1 k 2.2 k receiver stereo speaker line in external mic internal mic dc measurement ext spk-amp digital ground analog ground 10u to p vi e w notes: - vss1, vss2, vss3 and vss4 of the ak4671 should be distributed separately fro m the ground of external controllers. - all digital input pins s hould not be le ft floating. - when the ak4671 is ext mode (pmpll bit = ?0?), a resi stor and capacitor of the vcoc pin is not needed. - when the ak4671 is pll mode (pmpll bit = ?1?), a re sistor and capacitor of the vcoc pin is shown in table 4 . - when the ak4671 is used by master mode, lrck and bi ck pins are a hi-z state until m/s bit becomes ?1?. lrck and bick pins of the ak4671 should be pu lled-down or pulled-up by the resistor (about 100k ) externally to avoid the floating state. - a resistor and capacitor of the vcocbt pin is shown in table 76 . - after setting pdn pin = ?h?, the pcm i/f clock pins of ak4671 are a hi-z state until pmpcm bit becomes ?1?. the pcm i/f clock pins of master mode should be pulled-down or pulled-up by the resistor (about 100k ) externally to avoid the floating state. figure 108. typical connection diagram (internal full-differentila mic, exte rnal pseudo differential mic, recev ier output, 4-wire serial mode)
[ak4671] ms0666-e-02 2010/06 - 146 - 1. grounding and power supply decoupling the ak4671 requires careful attention to power suppl y and grounding arrangements. avdd, pvdd, savdd, dvdd, tvdd2 and tvdd3 are usually supplied from the syst em?s analog supply. if avdd, pvdd, savdd, dvdd, tvdd2 and tvdd3 are supplied separately, the power-up sequence is not critical. the pdn pin should be held to ?l? when power-up. the pdn pin should be set to ?h? after all power supplies are powered-up. in case that the pop noise should be avoided at receiver output , headphone output and line output, the ak4671 should be operated by the following reco mmended power-up/down sequence. 1) power-up - the pdn pin should be held to ?l? when power-up. the ak4671 should be reset by bringing the pdn pin ?l? for 150ns or more. - in case that the power supplies are separated in tw o or more groups, the power supply including dvdd should be powered on at first. 2) power-down - each power supplies should be powered off after the pdn pin is set to ?l?. - in case that the power supplies are separated in tw o or more groups, the power supply including dvdd should be powered off at last. vss1, vss2, vss3 and vss4 of the ak4671 should be c onnected to the analog ground plane. system analog ground and digital ground should be connected t ogether near to where the supplies ar e brought onto the printed circuit board. decoupling capacitors should be as near to the ak4671 as po ssible, with the small valu e ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noi se. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in orde r to avoid unwanted coupling into the ak4671. 3. analog inputs the mic, line and min inputs are single- ended. the input signal range scales with nominally at 0.6 x avdd vpp (typ) at mgnl=mgnr=0db and single-ended input, centered around the internal co mmon voltage (0.5 x avdd). the input signal should be ac coupled using a capac itor. the cut-off frequency is fc = 1/(2 rc). the ak4671 can accept input voltages from vss1 to avdd. 4. analog outputs the input data format for the dac is 2?s complement. th e output voltage is a positive full scale for 7fffh(@16bit) and a negative full scale for 8000h(@16bit). the ideal output is vcom voltage for 0000h(@16bit). vcom voltage is 0.5 x avdd (typ). when lout1, rout1, lout2, rout 2, lout3/lop and rout3/lon pins are single-ended output, these pins should be ac coupled using a capacitor. when rcp, rcn pins are full-differential out put, these pins should be connected directly to a receiver. (rcp, rcn pi ns should be not ac c oupled using a capacitor.)
[ak4671] ms0666-e-02 2010/06 - 147 - control sequence (audio) ? clock set up when adc or dac is powered-up, the clocks must be supplied. 1. pll master mode. bick pin lrck pin mcko bit (addr:02h, d2) pmpll bit (addr:02h, d0) 40msec(max) output (1) (6) power supply pdn pin pmvcm bit (addr:00h, d0) (2) (3) mcki pin (5) (4) input m/s bit (addr:02h, d1) mcko pin output (8) (7) 40msec(max) example: audio i/f format: msb justified (adc & dac) bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:00h, data:01h (2)addr:02h, data:22h addr:03h, data:02h addr:01h, data:f4h (4)addr:02h, data:27h mcko, bick and lrck output figure 109. clock set up sequence (1) (1) after power up, pdn pin = ?l? ? ?h?. ?l? time of 150ns or more is needed to reset the ak4671. the ak4671 should be operated as the recommended power-up/down sequence shown in ?system design (grounding and power supply decoupli ng)? to avoid pop noise at the r eceiver output, hea dphone output and lineout output. (2) dif1-0, pll3-0, fs3-0, bcko and m/s bits should be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered-up be fore the other block operates. (4) in case of using mcko output: mcko bit = ?1? (5) pll lock time is 40ms(max.) after pmpll bit changes fro m ?0? to ?1? and mcki is supplied from an external source. (6) the ak4671 starts to output the lrck and bick clocks after the pll becomes stable. then normal operation starts. (7) the invalid frequency is output from mcko pi n during this period if mcko bit = ?1?. (8) the normal clock is output from mcko pin afte r the pll is locked if mcko bit = ?1?.
[ak4671] ms0666-e-02 2010/06 - 148 - 2. pll slave mode (mcki pin) bick pin lrck pin mcko bit (addr:02h, d2) pmpll bit (addr:02h, d0) (1) power supply pdn pin pmvcm bit (addr:00h, d0) (2) (3) mcki pin (5) (4) input mcko pin output (7) (6) 40msec(max) (8) input example: audio i/f format: msb justified (adc & dac) bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:00h, data:01h (2)addr:03h, data:02h addr:01h, data:f4h (4)addr:02h, data:25h mcko output start bick and lrck input start figure 110. clock set up sequence (2) (1) after power up, pdn pin = ?l? ? ?h?. ?l? time of 150ns or more is needed to reset the ak4671. the ak4671 should be operated as the recommended power-up/down sequence shown in ?system design (grounding and power supply decoupli ng)? to avoid pop noise at the r eceiver output, hea dphone output and lineout output. (2) dif1-0, pll3-0 and fs3-0 bits s hould be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up be fore the other block operates. (4) enable mcko output: mcko bit = ?1? (5) pll starts after that the pmpll bit changes from ?0? to ?1? and pll refere nce clock (mcki pin) is supplied. pll lock time is 40ms(max.). (6) the normal clock is output fro m mcko during this period. (7) the invalid frequency is output from mcko after pll is locked. (8) bick and lrck clocks should be synchronized with mcko clock.
[ak4671] ms0666-e-02 2010/06 - 149 - 3. pll slave mode (lrck or bick pin) pmpll bit (addr:02h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:00h, d0) (2) (3) lrck pin bick pin (4) (5) input 4fs of example: audio i/f format : msb justified (adc & dac) pll reference clock: bick bick frequency: 64fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:01h (2) addr:03h, data:02h addr:01h, data:83h (4) addr:02h, data:01h figure 111. clock set up sequence (3) (1) after power up, pdn pin = ?l? ? ?h?. ?l? time of 150ns or more is needed to reset the ak4671. the ak4671 should be operated as the recommended power-up/down sequence shown in ?system design (grounding and power supply decoupli ng)? to avoid pop noise at the r eceiver output, hea dphone output and lineout output. (2) dif1-0, fs3-2 and pll3-0 bits s hould be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up be fore the other block operates. (4) pll starts after the pmpll bit cha nges from ?0? to ?1? and pll reference clock (lrck or bick pin) is supplied. pll lock time is 160ms(max.) when lrck is a pll reference clock. and pll lock time is 2ms(max.) when bick is a pll reference clock. (5) normal operation stats after that the pll is locked.
[ak4671] ms0666-e-02 2010/06 - 150 - 4. ext slave mode (1) power supply pdn pin pmvcm bit (addr:00h, d0) (2) (3) lrck pin bick pin (4) input (4) mcki pin input example: audio i/f format: msb justified (adc and dac) input mcki frequency: 256fs sampling frequency: 44.1khz mcko: disable (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:01h (2) addr:03h, data:02h addr:01h, data:00h mcki, bick and lrck input figure 112. clock set up sequence (4) (1) after power up, pdn pin = ?l? ? ?h?. ?l? time of 150ns or more is needed to reset the ak4671. the ak4671 should be operated as the recommended power-up/down sequence shown in ?system design (grounding and power supply decoupli ng)? to avoid pop noise at the r eceiver output, hea dphone output and lineout output. (2) dif1-0 and fs1-0 bits should be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up be fore the other block operates. (4) normal operation starts after the mc ki, lrck and bick are supplied.
[ak4671] ms0666-e-02 2010/06 - 151 - 5. ext master mode (1) power supply pdn pin pmvcm bit (addr:00h, d0) (3) (4) lrck pin bick pin (2) mcki pin input m/s bit (addr:02h, d1) output example: audio i/f format: msb justified (adc and dac) input mcki frequency: 256fs sampling frequency: 44.1khz mcko: disable (1) power supply & pdn pin = ?l? ? ?h? (4) addr:00h, data:01h (3) addr:03h, data:02h addr:01h, data:00h addr:02h, data:02h bick and lrck output (2) mcki input figure 113. clock set up sequence (5) (1) after power up, pdn pin = ?l? ? ?h?. ?l? time of 150ns or more is needed to reset the ak4671. the ak4671 should be operated as the recommended power-up/down sequence shown in ?system design (grounding and power supply decoupli ng)? to avoid pop noise at the r eceiver output, hea dphone output and lineout output. (2) mcki should be input. (3) after dif1-0 and fs2-0 bits are set, m/s bit shoul d be set to ?1?. then lrck and bick are output. (4) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up be fore the other block operates.
[ak4671] ms0666-e-02 2010/06 - 152 - mic input recording (stereo) fs3-0 bits (addr:01h, d7-4) mic control (addr:05h, d7-0) pmmicl/r bits pmadl/r bits (addr:00h, d5-2) adc internal state 1111 0000 55h aah power down initialize normal state power down 1059 / fs (1) (2) (7) alc state alc enable alc disable alc disable (5) alc control 1 (addr:16h) 00h 05h (3) alc control 2 (addr:14h) e1h e1h (4) alc control 3 (addr:17h) 15h 01h (8) (6) alc control 4 (addr:18h) 02h 03h 02h (9) pmmp bit (addr:00h, d1) example: pll master mode audio i/f format: msb justified (adc & dac) sampling frequency: 44.1khz pre mic amp: +15db mic power: on alc setting: refer to table 62 alc: enable ( 2 ) addr:05h, data: aah (3) addr:16h, data:05h (1) addr:01h, data:f4h (4) addr:14h, data:e1h (5) addr:17h, data:01h (7) addr:00h, data:3fh recording (8) addr:00h, data:01h (6) addr:18h, data:03h (9) addr:18h, data:02h figure 114. stereo mic input sequence (mic recording: lin1/rin1 micl/r adcl/r alc audio i/f sdto) this sequence is an example of alc setting at fs=44.1khz. if the parameter of the alc is changed, please refer to ? figure 62 ?. at first, clocks should be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bits). when the ak4671 is pll mode, mic and adc should be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up gain for mic-amp (addr: 05h) (3) set up timer select for alc (addr: 16h) (4) set up ref value for alc (addr: 14h) (5) set up lmth1-0, rgain1-0 and lmat1-0 bits (addr: 17h) (6) set up alc bit (addr: 18h) (7) power up mic and adc: pmmp = pmmicl = pmmicr = pmadl = pmadr bits = ?0? ?1? the initialization cycle time of adc is 1059/fs=24ms@fs=44.1khz. after the alc bit is set to ?1? and adc block is powered- up, the alc operation starts from ivol default value (0db). the time of offset voltage going to ?0? after the adc initialization cycle depends on both the time of analog input pin going to the common voltage and the time constant of the offset cancel digital hpf. this time can be shorter by using the following sequence: at first, pmvcm and pmmp bits should set to ?1?. then , the adc should be powered-up. the wait time to power-up the adc should be longer than 4 times of the time constant that is determined by the ac coupling capacitor at analog input pin and the internal input resistance. (8) power down mic and adc: pmmp = pmmicl = pmmicr = pmadl = pmadr bits = ?1? ?0? when the registers for the alc operation are not changed, al c bit may be keeping ?1?. the alc operation is disabled because the adc block is powered-down. if the registers for the alc operation are also changed when the sampling frequency is changed, it should be done after the ak4671 goes to the manual mode (alc bit = ?0?) or adc block is powered-down (pmadl = pmadr bits = ?0?). ivol gain is not reset when pmadl = pmadr bits = ?0?, and then ivol operation starts from the setting value wh en pmadl or pmadr bit is changed to ?1?. (9) alc disable: alc bit = ?1? ?0?
[ak4671] ms0666-e-02 2010/06 - 153 - headphone-amp output fs3-0 bits (addr:01h, d7-4) ovl/r7-0 bits (addr:1ah&1bh, d7-0) pml/ro2 bits (addr:10h, d1-0) muten bit (addr:10h, d2) lout2 pin rout2 pin 1111 0000 18h 28h normal output (1) eq bit (addr:18h, d3) 01 0 (3) (4) (11) pmdal/r bits (addr:00h, d7-6) (5) (10) (6) (8) (7) (9) pml/ro2s bits (addr:10h, d6-5) dachl/r bits (addr:0b&0ch, d0) (12) hpg3-0 bits (addr:08h, d7-4) 1011 1010 (2) exam ple : pll master mode audio i/f form at: m sb justified (adc & dac) sampling frequency: 44.1khz o v o lc b it = ?1? (d efault) d igital v olum e l evel: ? 8db hp volume level: ? 3db 5 band eq : enable (1) addr:01h, data:f4h (4) addr:1ah&1bh, data 28h (5) addr:00h, data c1h playback (3) addr:18h, data 0ah (8) addr:10h, data 63h (9) addr:10h, data 00h (6) addr:10h, data 63h (7) addr:10h, data 67h (10) a ddr:00h , d ata 01h (11) a ddr:18h , d ata 02h (2) a ddr:08h, data a5h addr:0bh&0ch, data 01h (12) addr:0bh&0ch, data 00h figure 115. headphone-amp output sequence (headphone playback: sdti audio i/f eq datt dacl/r lout2/rout2) at first, clocks should be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bits). when th e ak4671 is pll mode, dac and headphone-amp should be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up the path of ?sdti ? dac ? hp-amp?: dachl = dachr bits = ?0? ?1? set up analog volume for hp-amp (addr: 08h, hpg3-0 bits) (3) enable 5-band equalizer: eq bit = ?0? ? ?1? (boost amount is selected by addr = 50h-52h.) (4) set up the output digital volume (addr: 1ah and 1bh) when ovolc bit is ?1? (default), ovl 7-0 bits set the volume of both channels. after dac is powered-up, the digital volume changes from default value (0db) to the register setting value by the soft transition. (5) power up dac: pmdal = pmdar bits = ?0? ?1? (6) power up headphone-amp and mix-amp: pmlo2 = pmro2 = pmlo2s = pmro2s bits = ?0? ?1? output voltages of headphone-amp are still vss1. (7) rise up the common voltage of headphone-amp: muten bit = ?0? ?1? the rise time depends on avdd and the capacitor valu e connected with the mutet pin. when avdd=3.3v and the capacitor value is 1.0 f, the time constant is r = 250ms(max.). (8) fall down the common voltage of headphone-amp: muten bit = ?1? ?0? the fall time depends on avdd and the capacitor value connected with the mutet pin. when avdd=3.3v and the capacitor value is 1.0 f, the time constant is f = 250ms(max.). if the power supply is powered-off or headphone-amp is powered-down before the common voltage goes to vss2, the pop noise occurs. it takes twice of f that the common voltage goes to vss2. (9) power down headphone-amp and mix-amp: pmlo2 = pmro2 = pmlo2s = pmro2s bits = ?1? ?0? (10) power down dac: pmdal = pmdar bits = ?1? ?0? (11) disable 5-band equalizer: eq bit = ?1? ? ?0? (12) disable the path of ?dac headphone-amp?: dachl = dachr bits = ?1? ?0?
[ak4671] ms0666-e-02 2010/06 - 154 - stereo line output fs3-0 bits (addr:01h, d7-4) ovl/r7-0 bits (addr:1ah&1bh, d7-0) pmdal/r bits (addr:00h, d7-6) pml/ro3 bits (addr:11h, d1-0) 1111 0000 18h 28h lout3 pin rout3 pin (1) (3) (4) (2) dacsl/r bits (addr:0dh&0eh, d0) (9) normal output (6) lops3 bit (addr:11h, d2) (5) >300 ms (7) (8) >300 ms (10) pfmxl/r1-0 bits (addr:15h, d3-0) 0000 0101 l3vl1-0 bits (addr:11h, d7-d6) 10 01 pfsel bis (addr:1dh, d0) example: pll, master mode audio i/f format: msb justified (adc & dac) sampling frequency: 44.1khz ovolc bit = ?1?(default) digital volume level: ? 8db lineout volume level: ? 3db (1) addr:01h, data:f4h (2) addr:11h, data:40h addr:1dh, data:01h addr:15h, data:05h addr:0dh&0eh, data:01h (3) addr:1ah&1bh, data:28h (4) addr:11h, data:44h (5) addr:00h, data:c1h addr:11h, data:47h (6) addr:11h, data:43h playback (7) addr:11h, data:47h (8) addr:00h, data:01h addr:11h, data:44h (9) addr:0dh&0e, data:00h (10) addr:11h, data:40h figure 116. stereo lineout sequence (speaker playback: sdti audio i/f svola datt dacl/r lout3/rout3 external spk-amp) at first, clocks should be supplied according to ? clock set up ? sequence. (1) set up the sampling frequency (fs3-0 bits). when the ak4671 is pll mode, dac and stereo line-amp should be powered-up in consideration of pll lo ck time after the sampling frequency is changed. (2) set up the path of ?sdti ? dac ? stereo line-amp?: pfsel = ?0? ? ?1?, pfmxl1-0 = pfmxr1-0 bits = ?0000? ? ?0101?, dacsl = dacsr bits = ?0? ? ?1? set up analog volume for stereo line-amp (addr: 11h, l3vl1-0 bits) (3) set up the output digital volume (addr: 1ah and 1bh) when ovolc bit is ?1? (default), ovl 7-0 bits set the volume of both channels. after dac is powered-up, the digital volume changes from default value (0db) to the register setting value by the soft transition. (4) enter power-save mode of stereo line-amp: lops3 bit = ?0? ? ?1? (5) power-up dac and stereo line-amp: pmdal = pmdar = pmlo3 = pmro3 bits = ?0? ?1? lout3 and rout3 pins rise up to vcom voltage afte r pmlo3 and pmro3 bits are changed to ?1?. rise time is 300ms(max.) at c=1 f and avdd=3.3v. (6) exit power-save mode of stereo line-amp: lops3 bit = ?1? ? ?0? lops3 bit should be set to ?0? after lout3 and rout 3 pins rise up. stereo line-amp goes to normal operation by setting lops3 bit to ?0?. (7) enter power-save mode of stereo line-amp: lops3 bit: ?0? ? ?1? (8) power-down dac and stereo line-amp: pmdal = pmdar = pmlo3 = pmro3 bits = ?1? ?0? lout3 and rout3 pins fall down to vss1. fall time is 300ms(max.) at c=1 f and avdd=3.3v. (9) disable the path of ?dac ? stereo line-amp?: dacsl = dacsr bits = ?1? ? ?0? (10) exit power-save mode of stereo line-amp: lops3 bit = ?1? ? ?0? lops3 bit should be set to ?0? afte r lout3 and rout3 pins fall down.
[ak4671] ms0666-e-02 2010/06 - 155 - stop of clock master clock can be stopped wh en adc and dac are not used. 1. pll master mode external mcki pmpll bit (addr:02h, d0) mcko bit (addr:02h, d2) input (2) (1) (1) "1" or "0" example: audio i/f format: msb justified (adc & dac) bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz sampling frequency: 44.1khz (2) stop an external mcki (1) addr:02h, data:02h figure 117. clock stopping sequence (1) (1) power down pll: pmpll bit = ?1? ?0? stop mcko clock: mcko bit = ?1? ?0? (2) stop an external mcki clock. 2. pll slave (mcki pin) external mcki pmpll bit (addr:02h, d0) input (1) (2) mcko bit (addr:02h, d2) (1) example audio i/f format: msb justified (adc & dac) pll reference clock: mcki bick frequency: 64fs sampling frequency: 44.1khz (1) addr:02h, data:00h (2) stop the external clocks figure 118. clock stopping sequence (2) (1) power down pll: pmpll bit = ?1? ?0? stop mcko output: mcko bit = ?1? ?0? (2) stop the external master clock. 3. pll slave mode (lrck or bick pin) external bick pmpll bit (addr:02h, d0) input (1) (2) external lrck input (2) example audio i/f format: msb justified (adc & dac) pll reference clock: bick bick frequency: 64fs sampling frequency: 44.1khz (1) addr:02h, data:00h (2) stop the external clocks figure 119. clock stopping sequence (3) (1) power down pll: pmpll bit = ?1? ?0? (2) stop the external bick and lrck clocks
[ak4671] ms0666-e-02 2010/06 - 156 - 4. ext slave mode external lrck input (1) external bick input (1) external mcki input (1) example audio i/f format:msb justified(adc & dac) input mcki frequency:1024fs sampling frequency:44.1khz (1) stop the external clocks figure 120. clock stopping sequence (4) (1) stop the external mcki, bick and lrck clocks. 5. ext master mode lrck output bick output external mcki input (1) "h" or "l" "h" or "l" example audio i/f format:msb justified(adc & dac) input mcki frequency:1024fs sampling frequency:44.1khz (1) stop the external mcki figure 121. clock stopping sequence (5) (1) stop mcki clock. bick and lrck are fixed to ?h? or ?l?. power down power supply current can be shut down (typ. 20 a) by stopping clocks and setting pmvcm bit = ?0? after all blocks except for vcom are powered-down. power suppl y current can be also shut down (typ. 1 a) by stopping clocks and setting the pdn pin = ?l?. when the pdn pin = ?l?, the registers are initialized.
[ak4671] ms0666-e-02 2010/06 - 157 - control sequence (pcm) clock set up when adc or dac is powered-up, the clocks must be supplied. 1. pcm i/f a slave mode pmpcm bit (addr:53h, d2) internal clock (1) power supply pdn pin pmvcm bit (addr:00h, d0) (2) (3) synca pin bicka pin (4) (5) input 4fs of example: pcm i/f a format : linear, short frame (adc & dac) pllbt reference clock: synca synca frequency: 1fs2 sampling frequency: 8khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:01h (2) addr:02h, data:c0h addr:03h, data:12h addr:54h, data:00h addr:53h, data:00h addr:55h, data:00h (4) addr:53h, data:04h figure 122. clock set up sequence (1) (1) after power up, pdn pin = ?l? ? ?h?. ?l? time of 150ns or more is needed to reset the ak4671. the ak4671 should be operated as the recommended power-up/down sequence shown in ?system design (grounding and power supply decoupli ng)? to avoid pop noise at the r eceiver output, hea dphone output and lineout output. (2) btclk, lp, sdod, fmta1-0, lawa1-0, bckpa, msbsa, pllbt3-0 bits should be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up be fore the other block operates. (4) pllbt starts after the pmpcm bit changes from ?0? to ?1? and pllbt reference clock (synca or bicka pin) is supplied. pllbt lock time is 260ms(max.) wh en synca is a pllbt reference clock. and pllbt lock time is 40ms(max.) when bicka is a pllbt reference clock. (5) normal operation stats after that the pllbt is locked.
[ak4671] ms0666-e-02 2010/06 - 158 - 2. pcm i/f a master mode pmpcm bit (addr:53h, d2) internal clock (1) power supply pdn pin pmvcm bit (addr:00h, d0) (2) (3) syncb pin bickb pin (4) (5) input synca pin bicka pin (6) output 4fs of example: pcm i/f a format : linear, short frame (adc & dac) pllbt reference clock: syncb syncb frequency: 1fs2 sampling frequency: 8khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:01h (2) addr:02h, data:c0h addr:03h, data:12h addr:54h, data:00h addr:53h, data:00h addr:55h, data:00h (4) addr:53h, data:04h figure 123. clock set up sequence (2) (1) after power up, pdn pin = ?l? ? ?h?. ?l? time of 150ns or more is needed to reset the ak4671. the ak4671 should be operated as the recommended power-up/down sequence shown in ?system design (grounding and power supply decoupli ng)? to avoid pop noise at the r eceiver output, hea dphone output and lineout output. (2) btclk, lp, sdod, fmta1-0, lawa1-0, bckpa, msbsa, pllbt3-0 bits should be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up be fore the other block operates. (4) pllbt starts after the pmpcm bit changes from ?0? to ?1? and pllbt reference clock (syncb or bickb pin) is supplied. pllbt lock time is 260ms(max.) wh en syncb is a pllbt reference clock. and pllbt lock time is 40ms(max.) when bick b is a pllbt reference clock. (5) normal operation stats after that the pllbt is locked. (6) the invalid frequency is output from sync a and bicka after pllbt is locked.
[ak4671] ms0666-e-02 2010/06 - 159 - mic input phone call (mono) mic control 2 (addr:05h, d3-0) pmmicl bit pmadl bit (addr:00h, d4&d2) adc internal state 0101 1010 power down initialize normal state power down 1059 / fs (6) (4) hpf bit (addr:1dh, d4) 01 eq bit (addr:18h, d3) 01 (7) pmsra bit (addr:53h, d0) mic control 1 (addr:04h, d7-0) 00h 14h (1) pmmp bit (addr:00h, d1) hpfad bit (addr:1dh, d1) 01 (2) (5) ivl7-0 bits (addr:12h, d7-0) 91h bfh 0 (9) (8) pfmxl1-0 bits (addr:15h, d1-0) 00 01 (3) example: pcm i/f a: slave mode pcm i/f a format: linear, short frame (adc & dac) sampling frequency: 8khz pre mic amp: +15db mic power: on digital volume level: +17.25db adc hpf: enable 5 band eq: enable (1) addr:04h, data:14h addr:05h, data: aah (4) addr:18h, data:0ah (5) addr:12h, data:bfh (6) addr:00h, data:17h addr:53h, data:05h phone call (7) addr:00h, data:01h addr:53h, data:04h (2) addr:1dh, data:12h (9) addr:18h, data:02h (8) addr:1dh, data:00h (3) addr:15h, data:01h figure 124 . mono mic input sequence (phone call tx: in1+/in1- micl adcl hpf ivl eq src-a pcm i/f a sdtoa) at first, clocks should be supplied according to ? clock set up ? sequence. also, mic, adc and src-a should be powered-up in consideration of pllbt lock time. (1) set up signal select for mic input (addr: 04h) and gain for mic-amp (addr: 05h) (2) enable adc high pass filter: hpfad bit = ?0? ? ?1? enable the coefficient of high pass filter: hpf bit = ?0? ? ?1? (coefficient of wind-noise reduction filter is set by addr = 28h- 2bh.) this sequence is an example of hpf setting at fs2=8khz. th e coefficient should be set when hpfad = hpf bits = ?0? or pmadl = pmadr = pmdal = pmdar bits = ?0?. (3) set up the path of ?adc ? 5-band eq?: pfmxl1-0 bits = ?00? ? ?01? (4) enable 5-band equalizer: eq bit = ?0? ? ?1? (boost amount is selected by addr = 50h-52h.) (5) set up input volume (addr: 12h) when pmadl = pmadr bits = ?0?, ivl7-0 and ivr7-0 bits should be set to ?91h?(0db). (6) power up mic, adc and src-a: pmmp = pmmicl = pmadl = pmsra bits = ?0? ?1? the initialization cycle time of adc is 1059/fs2=132ms@fs2=8khz. the time of offset voltage going to ?0? after the adc initialization cycle depends on both the time of analog input pin going to the common voltage and the time constant of the offset cancel digital hpf. this time can be shorter by using the following sequence: at first, pmvcm and pmmp bits should set to ?1?. then , the adc should be powered-up. the wait time to power-up the adc should be longer than 4 times of the time constant that is determined by the ac coupling capacitor at analog input pin and the internal input resistance. (7) power down mic, adc and src-a: pmmp = pmmicl = pmadl = pmsra bits = ?1? ?0? ivol gain is not reset when pmadl = pmadr bits = ?0?, and then ivol operation starts from the setting value when pmadl or pmadr bit is changed to ?1?. (8) disable adc high pass filter : hpfad bit = ?1? ? ?0? disable the coefficient of high pass filter: hpf bit = ?1? ? ?0? (9) disable 5-band equalizer: eq bit = ?1? ? ?0?
[ak4671] ms0666-e-02 2010/06 - 160 - receiver-amp output ovr7-0 bits (addr:1bh, d7-0) pmdar bit (addr:00h, d7) pml/ro1 bits (addr:0fh, d1-0) 18h 28h rcp pin rcn pin (3) (4) (1) dacr bit (addr:0ah, d0) (10) normal output (6) lops1 bit (addr:0fh, d2) (5) (7) (8) (11) l1vl2-0 bits (addr:08h, d2-0) 101 100 pmsrb bit (addr:53h, d1) eq bit (addr:18h, d3) 01 0 (2) (9) srmxr1-0 bits (addr:15h, d7-6) 00 01 rcv bit (addr:0fh, d5) >1 ms example: pcm i/f a: slave mode pcm i/f a format : linear, short frame (adc & dac) sampling frequency: 8khz digital volume level: ? 8db rcv volume level: 0db 5 band eq: enable (1) addr:08h, data:b4h addr:15h, data:40h addr:0ah, data:01h addr:0fh, data:20h (3) addr:1bh, data:28h (4) addr:0fh, data:24h (5) addr:53h, data:06h addr:00h, data:81h addr:0fh, data:27h (6) addr:0fh, data:23h phone call (7) addr:0fh, data:27h (8) addr:53h, data:04h addr:00h, data:01h addr:0fh, data:24h (10) addr:0ah, data:00h (11) addr:0fh, data:20h (2) addr:18h, data:0ah (9) addr:18h, data:02h figure 125. receiver-amp output sequence (phone call rx: sdtia pcm i/f a src-b eq datt dacr rcp/rcn) at first, clocks should be supplied according to ? clock set up ? sequence. also, src-b, dac and receiver-amp should be powered-up in consideration of pllbt lock time. (1) set up the path of ?sdtia ? dac ? receiver-amp?: srmxr1-0 bits = ?00? ? ?01?, dacr bit = ?0? ? ?1?, rcv bit = ?0? ? ?1? set up analog volume for receiver-amp (addr: 08h, l1vl2-0 bits) (2) enable 5-band equalizer: eq bit = ?0? ? ?1? (boost amount is selected by addr = 50h-52h.) (3) set up the output digital volume (addr: 1bh) when ovolc bit is ?1? (default), ovl 7-0 bits set the volume of both channels. after dac is powered-up, the digital volume changes from default value (0db) to the register setting value by the soft transition. (4) enter power-save mode of receiver-amp: lops1 bit = ?0? ? ?1? (5) power-up src-b, dac and receiver-amp: pmsrb bit = pmdar = pmlo1 = pmro1 bits = ?0? ?1? rcn pin rise up to vcom voltage after pmlo 1 and pmro1 bits are changed to ?1?. (6) exit power-save mode of receiver-amp: lops1 bit = ?1? ? ?0? lops1 bit should be set to ?0? after pcn pin rise up. receiver-amp goes to normal operation by setting lops1 bit to ?0?. (7) enter power-save mode of receiver-amp: lops1 bit: ?0? ? ?1? (8) power-down src-b, dac and receiver-amp: pms rb bit = pmdar = pmlo1 = pmro1 bits = ?1? ?0? receiver-amp becomes to power-down mode. (9) disable 5-band equalizer: eq bit = ?1? ? ?0? (10) disable the path of ?dac ? receiver-amp?: dacr bit = ?1? ? ?0? (11) exit power-save mode of receiver-amp: lops1 bit = ?1? ? ?0? lops1 bit should be set to ?0? after receiver-amp power-down.
[ak4671] ms0666-e-02 2010/06 - 161 - mono line output ovr7-0 bits (addr:1bh, d7-0) pmdar bit (addr:00h, d7) pmro3 bit (addr:11h, d1) 18h 28h rout3 pin (3) (4) (1) dacsr bit (addr:0eh, d0) (10) normal output (6) lops3 bit (addr:11h, d2) (5) >300 ms (7) (8) >300 ms (11) l3vl1-0 bits (addr:11h, d7-d6) 10 01 pmsrb bit (addr:53h, d1) eq bit (addr:18h, d3) 01 0 (2) (9) srmxr1-0 bits (addr:15h, d7-6) 00 01 example: pcm i/f a: slave mode pcm i/f a format : linear, short frame (adc & dac) sampling frequency: 8khz digital volume level: ? 8db lineout volume level: ? 3db 5 band eq: enable (1) addr:11h, data:40h addr:15h, data:40h addr:0eh, data:01h (3) addr:1bh, data:28h (4) addr:11h, data:44h (5) addr:53h, data:06h addr:00h, data:81h addr:11h, data:46h (6) addr:11h, data:42h playback (7) addr:11h, data:46h (8) addr:53h, data:04h addr:00h, data:01h addr:11h, data:44h (10) addr:0eh, data:00h (11) addr:11h, data:40h (2) addr:18h, data:0ah (9) addr:18h, data:02h figure 126. mono lineout sequence (speaker playback: sdtia pcm i/f a src-b eq datt dacr rout3 external spk-amp) at first, clocks should be supplied according to ? clock set up ? sequence. also, src-b, dac and mono line-amp should be powered-up in consideration of pllbt lock time. (1) set up the path of ?sdtia ? dac ? mono line-amp?: srmxr1-0 bits = ?00? ? ?01?, dacsr bit = ?0? ? ?1? set up analog volume for mono line-amp (addr: 11h, l3vl1-0 bits) (2) enable 5-band equalizer: eq bit = ?0? ? ?1? (boost amount is selected by addr = 50h-52h.) (3) set up the output digital volume (addr: 1bh) when ovolc bit is ?1? (default), ovl 7-0 bits set the volume of both channels. after dac is powered-up, the digital volume changes from default value (0db) to the register setting value by the soft transition. (4) enter power-save mode of mono line-amp: lops3 bit = ?0? ? ?1? (5) power-up src-b, dac and mono line-amp: pmsrb = pmdar = pmro3 bits = ?0? ?1? rout3 pin rise up to vcom voltage after pmro3 bit is changed to ?1?. rise time is 300ms(max.) at c=1 f and avdd=3.3v. (6) exit power-save mode of mono line-amp: lops3 bit = ?1? ? ?0? lops3 bit should be set to ?0? after rout3 pin rise up. mono line-amp goes to normal operation by setting lops3 bit to ?0?. (7) enter power-save mode of mono line-amp: lops3 bit: ?0? ? ?1? (8) power-down src-b, dac and mono line-amp: pmsrb = pmdar = pmro3 bits = ?1? ?0? rout3 pin fall down to vss1. fall time is 300ms(max.) at c=1 f and avdd=3.3v. (9) disable 5-band equalizer: eq bit = ?1? ? ?0? (10) disable the path of ?dac ? mono line-amp?: dacsr bit = ?1? ? ?0? (11) exit power-save mode of mono line-amp: lops3 bit = ?1? ? ?0? lops3 bit should be set to ?0? after rout3 pin fall down.
[ak4671] ms0666-e-02 2010/06 - 162 - stop of clock master clock can be stopped wh en adc and dac are not used. 1. pcm i/f a slave mode external synca pmpcm bit (addr:53h, d2) input (1) (2) external bicka input (2) example pcm i/f a format : linear, short frame (adc & dac) pllbt reference clock: synca synca frequency: 1fs2 sampling frequency: 8khz (1) addr:53h, data:00h (2) stop the external clocks figure 127. clock stopping sequence (1) (1) power down pllbt: pmpcm bit = ?1? ?0? (2) stop the external synca and bicka clocks 2. pcm i/f a master mode external syncb pmpcm bit (addr:53h, d2) input (1) (2) external bickb input (2) bicka output synca output "h" or "l" "h" or "l" example pcm i/f a format : linear, short frame (adc & dac) pllbt reference clock: syncb syncb frequency: 1fs2 sampling frequency: 8khz (1) addr:53h, data:00h (2) stop the external clocks figure 128. clock stopping sequence (2) < example > (1) power down pllbt: pmpcm bit = ?1? ?0? (2) stop the external syncb and bickb clocks. s ynca and bicka are fixed to ?h? or ?l?. power down power supply current can be shut down (typ. 20 a) by stopping clocks and setting pmvcm bit = ?0? after all blocks except for vcom are powered-down. power suppl y current can be also shut down (typ. 1 a) by stopping clocks and setting the pdn pin = ?l?. when the pdn pin = ?l?, the registers are initialized.
[ak4671] ms0666-e-02 2010/06 - 163 - package 5.0 0.1 5.0 0.1 0.5 a b c d e f g 7 6 5 4 3 2 1 57 - 0.3 0.05 h j 9 8 0.08 s s 0.05 ab s b 0.5 m a 4.0 1.0max 0.25 0.05 material & lead finish package molding compound: epoxy , halogen (bromine and chlorine) free interposer material: bt resin solder ball material: snagcu
[ak4671] ms0666-e-02 2010/06 - 164 - marking 4671 x xxx a 1 xxxx: date code (4 digit) pin #a1 indication revision history date (yy/mm/dd) revision reason page contents 07/10/15 00 first edition 08/12/04 01 specification change 163 package molding compound was changed. 10/06/04 02 error correct 6 unused pi n: bicka, synca, bickb, syncb ?connect to vss4? ? ?when all pins are unused, these pins should be connected to vss4 and pmpcm bit must be always ?0?. when either pcm i/f a(bicka/ synca) or pcm i/f b(bickb/syncb) is used, unused pins are connected to pull-down/ up resistor of about 100k .? 104 table 86: msbsa, bckpa=?00? [msb of sdtoa is output by the falling edge (? ?) of synca.] ? [msb of sdtoa is output by next rising edge (? ?) of the falling edge (? ?) of bicka after the rising edge (? ?) of synca.] msbsa, bckpa=?01? [msb of sdtoa is output by the falling edge (? ?) of synca.] ? [msb of sdtoa is output by next falling edge (? ?) of the rising edge (? ?) of bicka after the rising edge (? ?) of synca.] msbsa, bckpa=?10? [msb of sdtoa is output by the rising edge (? ?) of the first bicka after the rising edge(? ?) of synca.] ? [msb of sdtoa is output by the 2nd rising edge (? ?) of bicka after the rising edge (? ?) of synca.]
[ak4671] ms0666-e-02 2010/06 - 165 - date (yy/mm/dd) revision reason page contents 10/06/04 02 error correct 104 table 86: msbsa, bckpa=?11? [msb of sdtoa is output by the falling edge (? ?) of the first bicka after the rising edge(? ?) of synca.] ? [msb of sdtoa is out put by the 2nd falling edge (? ?) of bicka after the rising edge (? ?) of synca.] table 87: msbsb, bckpb=?00? [msb of sdtob is output by the falling edge (? ?) of syncb.] ? [msb of sdtob is output by next rising edge (? ?) of the falling edge (? ?) of bickb after the rising edge (? ?) of syncb.] msbsb, bckpb=?01? [msb of sdtob is output by the falling edge (? ?) of syncb.] ? [msb of sdtob is output by next falling edge (? ?) of the rising edge (? ?) of bickb after the rising edge (? ?) of syncb.] msbsb, bckpb=?10? [msb of sdtob is output by the rising edge (? ?) of the first bickb after the rising edge(? ?) of syncb.] ? [msb of sdtob is output by the 2nd rising edge (? ?) of bickb after the rising edge (? ?) of syncb.] msbsb, bckpb=?11? [msb of sdtob is output by the falling edge (? ?) of the first bickb after the rising edge(? ?) of syncb.] ? [msb of sdtob is output by the 2nd falling edge (? ?) of bickb after the rising edge (? ?) of syncb.] 105 ~ 107 figure 84-91: arrow of synca and bicka was added.
[ak4671] ms0666-e-02 2010/06 - 166 - important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, a pplication circuits, software and other related inform ation contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporati on of these external circuits, applicati on circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein . akm assumes no liability for infringement of any patent, intellectual property, or other right s in the application or use of su ch information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by re presentative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said produc t in the absence of such notification.

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